Data generation apparatus, electronic device, and authentication system

1. A data generation apparatus comprising:

a memory space including a plurality of memory cells, each including a resistance change element;

a first circuit configured to supply the memory cells included in a first space that represents part of the memory space with a current or a voltage that causes a dielectric breakdown to occur in the resistance change element;

a second circuit configured to output a value read from the memory cells included in the first space; and

an ID generation circuit configured to generate an ID using the value output from the second circuit, wherein

the plurality of memory cells include pairs of memory cells, the pairs each including a first memory cell and a second memory cell,

the first circuit causes a dielectric breakdown to occur in the resistance change element in either the first memory cell or the second memory cell of each pair of memory cells,

the second circuit determines a bit value using values read from the first memory cell and the second memory cell of each pair of memory cells, and

the ID generation circuit generates the ID using the bit value determined by the second circuit.

2. The data generation apparatus according to claim 1 , wherein the first circuit controls a value or a flow time of the current or a value or an application time of the voltage to cause a dielectric breakdown to occur in the resistance change element in the memory cell included in the first space.

3. The data generation apparatus according to claim 1 , wherein the ID generation circuit identifies an address of a memory cell in which a dielectric breakdown occurs in the resistance change element using the value output from the second circuit and generates the ID using the identified address.

4. The data generation apparatus according to claim 1 , wherein

the first memory cell and the second memory cell each include a transistor,

the resistance change element in each of the first memory cell and the second memory cell is connected with the transistor, and

the transistor of each of first memory cell and the second memory cell is cross-coupled to the other such that a terminal of the transistor of the first cell connected with the resistance change element is connected with a gate of the transistor of the second cell, and a terminal of the transistor of the second cell connected with the resistance change element is connected with a gate of the transistor of the first cell.

5. The data generation apparatus according to claim 1 , wherein

the first memory cell and the second memory cell include transistors having gates coupled to each other to constitute a differential amplifier circuit, and

the resistance change element in each of the first memory cell and the second memory cell is connected with the transistor.

6. The data generation apparatus according to claim 1 , further comprising:

a third circuit configured to detect that a dielectric breakdown has occurred in the resistance change element, wherein

when the third circuit detects that a dielectric breakdown has occurred in the resistance change element, the first circuit stops the supply of the current or the voltage.

7. The data generation apparatus according to claim 1 , wherein the resistance change element includes a magnetic resistive junction.

8. The data generation apparatus according to claim 1 , wherein the ID generation circuit stores the generated ID in a second space that is different from the first space in the memory space.

9. The data generation apparatus according to claim 1 , wherein the first memory cell and the second memory cell are adjacent to each other.