MRAM-based chip identification with free random programming
A magnetoresistive random access memory (MRAM) device having chip identification using normal operating voltages is provided. No dedicated programming is needed. Instead, programming of the MRAM device is free and random and is a result of providing a magnetic via structure sufficiently close to the magnetic free layer of the magnetic junction tunnel (MTJ) structure such that the magnetic via structure projects a magnetic field that interacts with the magnetic free layer and aligns the magnetization of the magnetic free layer with the magnetization of the magnetic via structure. Thus, the orientation of the magnetization of both the magnetic via structure and the magnetic free layer are aligned in a same direction. The magnetization of the magnetic via structure can thus be used as a physical unclonable function and the MTJ structure can be used to read out this information.
1. A magnetoresistive random access memory (MRAM) device comprising:
a stack of, from bottom to top, a magnetic via structure and a first electrode;
a first interconnect dielectric material layer embedding both the magnetic via structure and the first electrode;
a magnetic tunnel junction (MTJ) structure located on the first electrode of the stack, wherein the MTJ structure comprises a tunnel barrier layer sandwiched between a magnetic free layer and a magnetic reference layer; and
a second electrode located on the MTJ structure, wherein the magnetic free layer of the MTJ structure has a magnetization vector aligned in a same direction as a magnetization vector of the magnetic via structure, the direction of the magnetization vector of the magnetic via structure is random and is dependent on an aspect ratio of the magnetic via structure and a distance between the magnetic via structure and the magnetic free layer, and the magnetic reference layer has a magnetization vector that can be in the same direction as, or a different direction than, the magnetization vector of both the magnetic free layer and the magnetic via structure, and wherein a read out of the magnetization vectors provides chip identification to a chip containing the MRAM device, wherein the aspect ratio of the magnetic via structure is greater than 2:1 and the distance between the magnetic via structure and the magnetic free layer is no more than 30 nm.
2. The MRAM device of claim 1 , further comprising a contact structure located on, and contacting a surface of, the second electrode.
3. The MRAM device of claim 2 , wherein the contact structure and the MTJ structure are both embedded in a second interconnect dielectric material layer.
4. The MRAM device of claim 1 , wherein the MTJ structure is a bottom pinned MTJ structure.
5. The MRAM device of claim 1 , wherein the MTJ structure is a top pinned MTJ structure.
6. The MRAM device of claim 1 , wherein the magnetic via structure is located directly beneath the first electrode.
7. The MRAM device of claim 1 , wherein the magnetic material of the magnetic via structure is compositionally the same as the magnetic material of the first electrode.
8. The MRAM device of claim 1 , wherein the magnetic material of the magnetic via structure compositionally differs from the magnetic material of the first electrode.
9. The MRAM device of claim 1 , wherein the magnetic via structure is composed of a magnetic material and the first electrode is composed of a non-magnetic, but electrically conductive material.
10. The MRAM device of claim 1 , wherein the magnetization vector of the magnetic reference layer is aligned in the same direction as the magnetization vector of both the magnetic via structure and the magnetic free layer, and the read out is 0.
11. The MRAM device of claim 1 , wherein the magnetization vector of the magnetic reference layer points in a different direction than the magnetization vector of both the magnetic via structure and the magnetic free layer and the read out is 1.
12. A magnetoresistive random access memory (MRAM) device comprising:
a stack of, from bottom to top, a first electrode and a magnetic via structure;
a first interconnect dielectric material layer embedding both the magnetic via structure and the first electrode;
a magnetic tunnel junction (MTJ) structure located on the magnetic via structure of the stack, wherein the MTJ structure comprises a tunnel barrier layer sandwiched between a magnetic free layer and a magnetic reference layer; and
a second electrode located on the MTJ structure, wherein the magnetic free layer of the MTJ structure has a magnetization vector aligned in a same direction as a magnetization vector of the magnetic via structure, the direction of the magnetization vector of the magnetic via structure is random and is dependent on an aspect ratio of the magnetic via structure and a distance between the magnetic via structure and the magnetic free layer, and the magnetic reference layer has a magnetization vector that can be in the same direction as, or a different direction than, the magnetization vector of both the magnetic free layer and the magnetic via structure, and wherein a read out of the magnetization vectors provides chip identification to a chip containing the MRAM device, wherein the aspect ratio of the magnetic via structure is greater than 2:1 and the distance between the magnetic via structure and the magnetic free layer is no more than 30 nm.
13. The MRAM device of claim 12 , wherein the magnetic via structure is composed of a magnetic material and the first electrode is composed of a non-magnetic, but electrically conductive material.
14. The MRAM device of claim 12 , wherein the magnetic via structure and the first electrode are both composed of a magnetic material.
15. A non-volatile memory (NVM) array comprising:
a plurality of spaced apart magnetoresistive random access memory (MRAM) devices located on a substrate, wherein each MRAM device of the plurality of MRAM devices comprises a magnetic via structure, a first electrode, a first interconnect dielectric material layer embedding both the magnetic via structure and the first electrode, a magnetic tunnel junction (MTJ) structure located above both the first via structure and the first electrode, wherein the MTJ structure comprises a tunnel barrier layer sandwiched between a magnetic free layer and a magnetic reference layer, and a second electrode located on the MTJ structure, wherein the magnetic free layer of the MTJ structure has a magnetization vector aligned in a same direction as a magnetization vector of the magnetic via structure, the direction of the magnetization vector of the magnetic via structure is random and is dependent on an aspect ratio of the magnetic via structure and a distance between the magnetic via structure and the magnetic free layer, and the magnetic reference layer has a magnetization vector that can be in the same direction as, or a different direction than, the magnetization vector of both the magnetic free layer and the magnetic via structure, and wherein a read out of the magnetization vectors provides chip identification to a chip containing the NVM array, wherein the aspect ratio of the magnetic via structure is greater than 2:1 and the distance between the magnetic via structure and the magnetic free layer is no more than 30 nm.
16. The NVM array of claim 15 , wherein the magnetic reference layer of a first set of MRAM devices has a magnetization that is the same as the magnetization of both the magnetic via structure and the magnetic free layer in the first set of MRAM devices, and wherein the magnetic reference layer of a second set of MRAM devices has a magnetization that differs from the magnetization of both the magnetic via structure and the magnetic free layer in the second set of MRAM devices.
17. The NVM array of claim 15 , wherein the magnetic via structure is located directly beneath the first electrode.
18. The NVM array of claim 15 , wherein the magnetic via structure is located directly above the first electrode.