Semiconductor device having air gap and method for manufacturing the same, memory cell having the same and electronic device having the same

1. A method for fabricating a semiconductor device, comprising: forming a plurality of first isolation trenches and a plurality of line-shaped active regions by etching a semiconductor substrate;

forming a line-shaped device isolation region in each of the plurality of first isolation trenches;

forming a plurality of second isolation trenches extending in a second direction by etching the plurality of line-shaped active regions and the plurality of line-shaped device isolation regions;

forming a connection trench to connect the plurality of second isolation trenches to each other; and

forming a shielding line in each of the plurality of second isolation trenches;

forming a shielding line interconnection in the connection trench;

after the forming of the shielding line and the shielding line interconnection, forming a

bit line trench extending in a first direction by etching the plurality of line-shaped active regions

and the plurality of line-shaped device isolation regions;

forming a buried bit line in the bit line trench;

forming a bulb-shaped body trench by etching the bottom surface of the bit line trench; and

forming only a punch-through preventing layer in the bulb-shaped body trench.

2. The method of claim 1 , wherein the forming of the plurality of second isolation trenches includes:

etching the plurality of line-shaped active regions to define a plurality of island-shaped active regions; and

etching the plurality of line-shaped device isolation regions to define a plurality of first device isolation regions.

3. The method of claim 1 , wherein the forming of the plurality of second isolation trenches and the forming of the connection trench are performed substantially at the same time.

4. The method of claim 1 , wherein the forming of the shielding line and the shielding line interconnection comprises:

forming a line layer to cover the plurality of second isolation trenches and the connection trench;

forming a shield layer over the liner layer, wherein the shield layer fills the plurality of second isolation trenches and the connection trench; and

etching back the shield layer.

5. The method of claim 4 , wherein the shield layer comprises a boron-doped polysilicon layer.

6. The method of claim 2 , further comprising, after the forming of the shielding line and the shielding line interconnection:

forming a gate trench by etching each of the plurality of island-shaped active regions and each of the plurality of first device isolation regions; and

forming a gate electrode in the gate trench.

7. The method of claim 6 , wherein the forming of the gate trench comprises:

forming a vertical trench in a direction crossing the buried bit line;

forming a sacrificial spacer over a sidewall of the vertical trench; and

forming a bulb-shaped trench by etching the bottom portion of the vertical trench through an isotropic etching process,

wherein the bulb-shaped trench communicates with the vertical trench.

8. The method of claim 7 , wherein the forming of the gate electrode comprises:

forming a first gate conductive layer in the bulb-shaped trench;

forming a second gate conductive layer in a lower portion of the vertical trench and over the first gate conductive layer;

forming a gate spacer on a sidewall of a upper portion of the vertical trench and over the second gate conductive layer; and

etching the second gate conductive layer and the first gate conductive layer using the gate spacer as a barrier.

9. The method of claim 8 , wherein the first gate conductive layer comprises a metallic material, and the second gate conductive layer comprises polysilicon.