IP Library Granted Patent US 10,008,569
Granted Patent B2
US 10,008,569 · App. 15/259,060 · Granted Jun 26, 2018

Semiconductor device and method for fabricating the same

Inventors: Chih-Kai Hsu (Tainan, TW); Ssu-I Fu (Kaohsiung, TW); Yu-Hsiang Hung (Tainan, TW); Wei-Chi Cheng (Kaohsiung, TW); Jyh-Shyang Jenq (Pingtung County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/0847H01L29/42356H01L29/42368H01L29/66545H01L29/66636H01L29/78
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Quick Facts
Patent No.
US 10,008,569
App. No.
15/259,060
Granted
Jun 26, 2018
Kind
B2
Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a recess is formed adjacent to the gate structure, a buffer layer is formed in the recess, and an epitaxial layer is formed on the buffer layer. Preferably, the buffer layer includes a crescent moon shape.

Claims (15)

1. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate;

a buffer layer adjacent to the gate structure, wherein the buffer layer comprises a crescent moon shape and the buffer layer comprises an inner curve and an outer curve intersect on a top surface of the substrate, and each of the inner curve and the outer curve intersect on the top surface of the substrate comprises a completely curved surface; and

an epitaxial layer on the buffer layer.

2. The semiconductor device of claim 1 , further comprising:

a spacer adjacent to the gate structure; and

the buffer layer adjacent to the spacer.

3. The semiconductor device of claim 2 , wherein the buffer layer comprises a first width and a second width directly under the spacer, wherein the second width is greater than the first width.

4. The semiconductor device of claim 3 , wherein the first width is between 3 nm to 7 nm.

5. The semiconductor device of claim 3 , wherein the second width is between 5 nm to 9 nm.

6. The semiconductor device of claim 1 , wherein a bottom surface of the epitaxial layer comprises a curve.

7. The semiconductor device of claim 6 , wherein the buffer layer comprises a vertical thickness directly under a valley point of the curve.

8. The semiconductor device of claim 7 , wherein the vertical thickness is between 7 nm to 11 nm.

9. The semiconductor device of claim 1 , wherein a top surface of the epitaxial layer is even with a top surface of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2016
From: HSU, CHIH-KAI; FU, SSU-I; HUNG, YU-HSIANG; CHENG, WEI-CHI; JENQ, JYH-SHYANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 039665/0092 →
Priority Claims (1)
TW 105125383 A · Aug 10, 2016 · national
Continuity (1)
Related Publication 20180047810A1 · Feb 15, 2018
Cited By (1)
US 12,532,721