Semiconductor memory device with variable resistance elements
In general, according to one embodiment, a semiconductor memory device includes: first and second variable resistance elements provided above a semiconductor layer; a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements; and a first interconnect extending in a first direction and provided on the first insulation layer, at least a portion of the first interconnect being opposed to the side surfaces of the first and second variable resistance elements via the first insulation layer.
1. A semiconductor memory device comprising:
first and second variable resistance elements provided above a semiconductor layer;
a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements;
a first interconnect extending in a first direction and provided on the first insulation layer, at least a portion of the first interconnect being opposed to the side surfaces of the first and second variable resistance elements via the first insulation layer;
a first transistor including first and second diffusion layers provided in the semiconductor layer, a gate insulation film, and a gate electrode;
a first plug coupling the first diffusion layer and the first variable resistance element; and
a second plug coupling the second diffusion layer and the first interconnect,
wherein a portion of a side surface of the second plug is in contact with the first interconnect.
2. The device according to claim 1 , wherein:
each of the first and second variable resistance elements is a magnetic tunnel junction (MTJ) element,
the MTJ element includes a magnesium oxide (MgO) layer, and
a level of a bottom surface of the MgO layer is between levels of a bottom surface and a top surface of the first interconnect.
3. A semiconductor memory device comprising:
first and second variable resistance elements provided above a semiconductor layer;
a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements;
a first interconnect extending in a first direction and provided on the first insulation layer, at least a portion of the first interconnect being opposed to the side surfaces of the first and second variable resistance elements via the first insulation layer;
a first transistor including first and second diffusion layers provided in the semiconductor layer, a gate insulation film, and a gate electrode;
a first plug coupling the first diffusion layer and the first variable resistance element;
a second plug coupling the second diffusion layer and the first interconnect;
third and fourth plugs coupled to the first and second variable resistance elements, respectively; and
second and third interconnects extending in the first direction and provided on the third and fourth plugs, respectively,
wherein a level of a bottom surface of the first interconnect differs from levels of bottom surfaces of the second and third interconnects.
4. The device according to claim 3 , wherein:
each of the first and second variable resistance elements is a magnetic tunnel junction (MTJ) element,
the MTJ element includes a magnesium oxide (MgO) layer, and
a level of a bottom surface of the MgO layer is between levels of the bottom surface and a top surface of the first interconnect.