IP Library Granted Patent US 10,056,545
Granted Patent B2
US 10,056,545 · App. 15/262,923 · Granted Aug 21, 2018

Sidewall-type memory cell

Inventors: Justin Hiroki Sato (West Linn, OR); Bomy Chen (Newark, CA); Sonu Daryanani (Tempe, AZ)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H01L45/1226H01L45/08H01L45/085H01L45/1253H01L45/1273H01L45/1675
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Quick Facts
Patent No.
US 10,056,545
App. No.
15/262,923
Granted
Aug 21, 2018
Kind
B2
Abstract

A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Claims (37)

1. A cell for a resistive memory, comprising:

a bottom electrode formed over an underlying substrate and having a bottom electrode thickness;

a top electrode layer defining a sidewall; and

an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and the top electrode sidewall via the electrolyte layer; and

wherein the bottom electrode layer extends generally horizontally with respect to the underlying substrate, and the top electrode sidewall extends non-horizontally with respect to the underlying substrate,

wherein the top electrode layer includes a first portion located laterally outwardly from a lateral edge of the bottom electrode layer, and

wherein a distance between the first portion of the top electrode layer to the underlying substrate is less than the bottom electrode thickness.

2. The cell according to claim 1 , wherein the top electrode sidewall defines a ring shape extending around an outer perimeter of the bottom electrode.

3. The cell according to claim 2 , wherein the top electrode layer comprises a covering portion extending over and parallel to the bottom electrode.

4. The cell according to claim 1 , wherein the electrolyte layer comprises a sidewall extending non-horizontally with respect to the underlying substrate, and wherein the conductive path is defined through the electrolyte sidewall.

5. The cell according to claim 4 , wherein the electrolyte layer sidewall extends parallel to the non-horizontal top electrode sidewall.

6. The cell according to claim 5 , wherein the electrolyte layer sidewall defines a ring extending radially inside the top electrode layer.

7. The cell according to claim 1 , wherein the top electrode sidewall extends at an angle relative to the underlying substrate, the angle being between 30 and 90 degrees (non-inclusive).

8. The cell according to claim 1 , wherein the top electrode sidewall extends at an angle relative to the underlying substrate, the angle being between 60 and 90 degrees (non-inclusive).

9. The cell according to claim 1 , wherein the top electrode sidewall extends at an angle relative to the underlying substrate, the angle being between 45 and 85 degrees (non-inclusive).

10. The cell according to claim 1 , wherein the top electrode sidewall extends perpendicular relative to the underlying substrate.

11. The cell according to claim 1 , wherein the bottom electrode layer is formed directly on the underlying substrate.

12. The cell according to claim 11 , wherein the top electrode layer is spaced apart from the underlying substrate by a portion of the electrolyte layer.

13. The cell according to claim 1 , wherein the cell is configured such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction between the bottom electrode and the top electrode sidewall.

14. The cell according to claim 1 , wherein the cell is configured such that when a positive bias-voltage is applied to the cell, a conductive path grows in a generally horizontal between the bottom electrode and the top electrode sidewall.

15. The cell according to claim 1 , wherein the bottom electrode has the shape of a flat circular electrode disk.

16. A method of forming a sidewall-type resistive memory cell, the method comprising:

depositing a bottom electrode layer having a bottom electrode thickness over a horizontally extending substrate;

forming a mask layer over the bottom electrode layer;

patterning the bottom electrode layer and the mask layer to define a bottom electrode and mask region;

depositing an electrolyte layer; and

forming a top electrode such that a sidewall of the top electrode extends non-horizontally with respect to the horizontal substrate, with the electrode layer arranged between the bottom electrode and the top electrode layer sidewall, wherein the top electrode layer includes a first portion located laterally outwardly from a lateral edge of the bottom electrode layer, and wherein a distance between the first portion of the top electrode layer to the underlying substrate is less than the bottom electrode thickness.

17. The method according to claim 16 , further comprising forming the top electrode such that the top electrode sidewall defines a ring shape extending around an outer perimeter of the bottom electrode.

18. The method according to claim 16 , wherein the top electrode sidewall extends at an angle relative to the horizontal substrate, the angle being between 30 and 90 degrees (non-inclusive).

19. The method according to claim 16 , wherein the top electrode sidewall extends at an angle relative to the horizontal substrate, the angle being between 60 and 90 degrees (non-inclusive).

20. The method according to claim 16 , wherein the top electrode sidewall extends at an angle relative to the horizontal substrate, the angle being between 45 and 85 degrees (non-inclusive).

21. The method according to claim 16 , wherein the top electrode sidewall extends perpendicular relative to the horizontal substrate.

22. The method according to claim 16 , comprising forming the bottom electrode directly on the substrate layer.

23. The method according to claim 22 , wherein the top electrode layer is spaced apart from the substrate layer by a portion of the electrolyte layer.

24. The method according to claim 16 , further comprising applying a positive bias-voltage is applied to the cell such that a conductive path grows in a non-vertical direction between the bottom electrode and the first portion of the top electrode sidewall located laterally outwardly from a lateral edge of the bottom electrode layer.

25. The method according to claim 16 , further comprising applying a positive bias-voltage is applied to the cell such that a conductive path grows in a generally horizontal direction between the bottom electrode and the first portion of the top electrode sidewall located laterally outwardly from a lateral edge of the bottom electrode layer.

26. The method according to claim 16 , wherein the bottom electrode has the shape of a flat circular electrode disk.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2016
From: SATO, JUSTIN HIROKI; CHEN, BOMY; DARYANANI, SONU
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 039997/0540 →
Continuity (2)
Continuation 14183831 · Feb 19, 2014
Related Publication 20160380192A1 · Dec 29, 2016
Cited By (1)
US 12,562,225