Fan-out semiconductor package for packaging semiconductor chip and capacitors

1. A fan-out semiconductor package comprising:

a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface;

a first capacitor disposed adjacently to the semiconductor chip;

an encapsulant at least partially encapsulating the inactive surface of the semiconductor chip and the first capacitor;

a first connection member disposed on the encapsulant, the first capacitor, and the active surface of the semiconductor chip, and

a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed,

wherein the first connection member includes a redistribution layer electrically connected to one of the connection pads of the semiconductor chip, the first capacitor, and the second capacitor, and

the first capacitor and the second capacitor are electrically connected to the one of the connection pads of the semiconductor chip through a common power wiring of the redistribution layer.

2. The fan-out semiconductor package of claim 1 , wherein C 1 is equal to C 2 , in which C 1 and C 2 are capacitances of the first and second capacitors, respectively.

3. The fan-out semiconductor package of claim 1 , wherein t 1 is greater than t 2 , in which t 1 and t 2 are thicknesses of the first and second capacitors, respectively.

4. The fan-out semiconductor package of claim 1 , wherein L 1 is equal to L 2 , in which L 1 and L 2 are equivalent series inductances (ESL) of the first and second capacitors, respectively.

5. The fan-out semiconductor package of claim 1 , wherein R 1 is equal to R 2 , in which R 1 and R 2 are equivalent series resistances (ESR) of the first and second capacitors, respectively.

6. The fan-out semiconductor package of claim 1 , wherein the first and second capacitors are connected to each other in parallel.

7. The fan-out semiconductor package of claim 1 , further comprising a passivation layer disposed on the other surface of the first connection member opposing the one surface of the first connection member on which the semiconductor chip is disposed and having openings exposing at least a portion of a wiring of the redistribution layer,

wherein the second capacitor is disposed on a surface of the passivation layer.

8. The fan-out semiconductor package of claim 7 , further comprising connection terminals disposed in the openings of the passivation layer,

wherein the connection terminals are disposed to surround the second capacitor and are electrically connected to other connection pads of the connection pads of the semiconductor chip.

9. The fan-out semiconductor package of claim 1 , further comprising a second connection member having a through-hole disposed on the second connection member,

wherein the semiconductor chip and the first capacitor are disposed in the through-hole,

the encapsulant covers an upper surface of the second connection member, and extends continuously from the upper surface of the second connection member and the inactive surface of the semiconductor chip to directly contact with the first connection member by passing the through-hole,

the encapsulant directly covers upper and side surfaces of the first capacitor and side surfaces of the semiconductor chip connecting the active and inactive surfaces to each other, and

a lower surface of the first capacitor opposing the upper surface of the first capacitor is in contact with the first connection member, and a lower surface of the second connection member opposing the upper surface of the second connection member is in contact with the first connection member.

10. The fan-out semiconductor package of claim 9 , wherein the second connection member includes a first insulating layer, a first redistribution layer contacting the first connection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and

the first and second redistribution layers are electrically connected to the connection pads.

11. The fan-out semiconductor package of claim 10 , wherein the second connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and

the third redistribution layer is electrically connected to the connection pads.

12. The fan-out semiconductor package of claim 10 , wherein a distance between the redistribution layer of the first connection member and the first redistribution layer is greater than that between the redistribution layer of the first connection member and the connection pads.

13. The fan-out semiconductor package of claim 10 , wherein the first redistribution layer is thicker than the redistribution layer of the first connection member.

14. The fan-out semiconductor package of claim 10 , wherein a lower surface of the first redistribution layer is disposed on a level above lower surfaces of the connection pads.

15. The fan-out semiconductor package of claim 11 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

16. The fan-out semiconductor package of claim 9 , wherein the second connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and

the first to third redistribution layers are electrically connected to the connection pads.

17. The fan-out semiconductor package of claim 16 , wherein the second connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and

the fourth redistribution layer is electrically connected to the connection pads.

18. The fan-out semiconductor package of claim 16 , wherein the first insulating layer is thicker than the second insulating layer.

19. The fan-out semiconductor package of claim 16 , wherein the third redistribution layer is thicker than the redistribution layer of the first connection member.

20. The fan-out semiconductor package of claim 16 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

21. The fan-out semiconductor package of claim 16 , wherein a lower surface of the third redistribution layer is disposed on a level below lower surfaces of the connection pads.

22. The fan-out semiconductor package of claim 1 , wherein the first connection member includes an insulating layer in direct contact with the first capacitor, and vias penetrating through the insulating layer and directly connected to the connection pads of the semiconductor chip and the first capacitor, respectively.

23. The fan-out semiconductor package of claim 22 , wherein two of the vias respectively connected to the first capacitor and the one of the connection pads of the semiconductor chip are directly connected to the common power wiring.

24. The fan-out semiconductor package of claim 1 , wherein in a stacking direction of the first connection member and the semiconductor chip, the common power wiring overlaps with the one of the connection pads of the semiconductor chip, at least a portion of the first capacitor, and at least a portion of the second capacitor.