Three-dimensional memory device with amorphous barrier layer and method of making thereof

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate; and

memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel laterally surrounded by the memory film,

wherein each of the electrically conductive layers comprises:

a layer stack including a polycrystalline titanium nitride layer and an amorphous, electrically conductive barrier layer; and

a metal fill material layer spaced from the insulating layers and the memory stack structures by the layer stack, the metal fill material layer comprising an elemental metal, and the metal fill material layer is located in direct contact with the amorphous, electrically conductive barrier layer, and spaced from the polycrystalline titanium nitride layer by the amorphous, electrically conductive layer;

wherein the polycrystalline titanium nitride layer directly contacts the memory stack structures; and

the amorphous, electrically conductive barrier layer contacts the metal fill material layer.

2. The three-dimensional memory device of claim 1 , wherein:

each of the memory stack structures comprises a charge storage layer and a tunneling dielectric layer that contacts a respective vertical semiconductor channel; and

each of the electrically conductive layers comprises a control gate electrode of the memory device.

3. The three-dimensional memory device of claim 2 , further comprising a backside blocking dielectric layer located between the electrically conductive layers and the insulating layers and continuously extending from a bottommost layer in the alternating stack to a topmost layer within the alternating stack, wherein each of the electrically conductive barrier layers contacts the backside blocking dielectric layer.

4. The three-dimensional memory device of claim 1 , further comprising:

drain regions contacting respective vertical semiconductor channels;

a source region located in an upper portion of the substrate;

semiconductor channels extending between the source region and the drain regions and including the vertical semiconductor channels of the memory stack structures;

an insulating spacer located at a periphery of a backside trench that extends through the alternating stack; and

a backside contact via structure located in the insulating spacer and contacting the source region,

wherein each of the electrically conductive barrier layers contacts an outer sidewall of the insulating spacer.

5. The three-dimensional memory device of claim 1 , wherein the amorphous, electrically conductive barrier layer comprises an amorphous oxygen-containing titanium compound, and the metal fill material layer comprises tungsten.

6. The three-dimensional memory device of claim 5 , wherein the amorphous oxygen-containing titanium compound is amorphous titanium oxide.

7. The three-dimensional memory device of claim 5 , wherein the amorphous oxygen-containing titanium compound is amorphous titanium oxynitride.

8. The three-dimensional memory device of claim 1 , wherein each of the at least one elemental metal is selected from tungsten, cobalt, ruthenium, titanium, and tantalum.

9. The three-dimensional memory device of claim 1 , wherein the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack, and the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack.

10. The three-dimensional memory device of claim 1 , wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises:

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

11. The three-dimensional memory device of claim 1 , wherein:

the polycrystalline titanium nitride layer includes columnar grain boundaries; and

the amorphous, electrically conductive barrier layer is free of columnar grain boundaries.