Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a standard cell

1. A method, comprising:

determining a first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell;

forming a dielectric feature over said first MOL interconnect feature at said first location; and

forming said metal feature over said dielectric feature, said dielectric feature providing a predetermined amount of voltage isolation between said first MOL interconnect feature and said metal feature, wherein forming said metal feature over said dielectric feature comprises:

forming said first MOL interconnect feature and a second MOL interconnect feature;

performing a post-fill chemical-mechanical process;

depositing a dielectric layer over said first and second MOL features;

forming an etch-resistant formation above said first location;

performing an etch process for removing a portion of said dielectric layer for forming said dielectric feature;

depositing an inter-layer dielectric (ILD) layer;

performing a metal trench patterning process in said ILD layer for forming a trench comprising said dielectric feature; and

depositing a metal material in said trench for forming said metal feature, wherein said metal feature is in contact with said second MOL interconnect feature and not in contact with said first MOL interconnect feature.

2. The method of claim 1 , wherein forming said etch-resistant formation comprises:

depositing a photoresist layer; and

performing a photolithography process for forming said etch-resistant formation above said first location.

3. The method of claim 1 , wherein further comprising:

forming a first gate formation on a first side of said first and second MOL interconnect features;

forming a second gate formation on a second side of said first and second MOL interconnect features wherein said first and second MOL interconnect features are between said first and second gate formations; and

forming said metal feature above said first and second MOL interconnect features and above said first and second gate features, wherein said metal feature only makes contact with said second MOL interconnect feature.

4. The method of claim 3 , wherein forming said metal feature comprises forming a third MOL interconnect feature for providing a connection between said first gate and said second gate and not connecting said third MOL feature to said first MOL interconnect feature.

5. The method of claim 4 , wherein forming said third MOL interconnect feature comprises forming a CB feature.

6. The method of claim 1 , wherein forming said first MOL interconnect feature comprises forming a first CA feature, and wherein forming said second MOL interconnect feature comprises forming a second CA feature.

7. The method of claim 1 , forming said metal feature comprises forming a Metal-1 layer (M1) metal feature.

8. The method of claim 1 , wherein said dielectric feature provides a predetermined capacitive parameter between said first MOL interconnect feature and said metal feature.

9. A method, comprising:

forming a first gate structure and a second gate structure in an integrated circuit;

forming a source structure and a drain structure;

forming a first middle of line (MOL) interconnect feature between said first and second gate structures;

forming a second MOL interconnect feature for operatively coupling said first and second gate structures;

forming a metal feature for coupling said source and drain structures; and

forming a cover layer over at least a portion of said first and second MOL interconnect features for providing a predetermined amount of voltage isolation between said first MOL interconnect feature and said metal feature, wherein forming said cover layer comprises:

depositing a dielectric layer over said first and second MOL features;

forming said cover layer above said first and second MOL features;

performing an etch process for removing a portion of said cover layer not overlying said portion of said first and second MOL interconnect features;

depositing an inter-layer dielectric (ILD) layer;

performing a metal trench patterning process in said ILD layer for forming a trench comprising said cover layer; and

depositing a metal material in said trench for forming said metal feature.

10. The method of claim 9 , further comprising:

forming a first active area, wherein said source region is formed in said first active area;

forming a second active area, wherein said drain region is formed in said second active area;

forming a first power rail proximate said first active area; and

forming a second power rail proximate said second active area.

11. The method of claim 9 , wherein forming said etch-resistant formation comprises:

depositing a photoresist layer; and

performing a photolithography process for forming said etch-resistant formation.

12. The method of claim 9 , wherein forming said first MOL interconnect feature comprises forming a CA feature, and forming said second MOL interconnect feature comprises forming a CB bar.

13. The method of claim 9 , wherein forming said metal feature comprises forming a Metal-1 layer (M1) metal feature.