IP Library Granted Patent US 10,128,239
Granted Patent B2
US 10,128,239 · App. 15/294,906 · Granted Nov 13, 2018

Preserving channel strain in fin cuts

Inventors: Andrew M. Greene (Albany, NY); Dechao Guo (Niskayuna, NY); Ravikumar Ramachandran (Pleasantville, NY); Rajasekhar Venigalla (Hopewell Junction, NY)
Assignee: International Business Machines Corporation
H01L27/0886H01L21/3081H01L21/30625H01L21/31116H01L21/31144H01L21/823431H01L21/823468H01L21/823481H01L29/0649H01L29/6653H01L29/6656H01L29/66545
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,128,239
App. No.
15/294,906
Granted
Nov 13, 2018
Kind
B2
Abstract

A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.

Claims (33)

1. A method of forming a semiconductor structure, comprising:

forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure, the finFET structure comprising one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure;

performing a fin cut by removing a portion of at least one of the fins, the portion of said at least one fin being determined by an exposed area of the fin cut mask, the exposed area of the fin cut mask comprising at least a portion of said at least one fin between a first dummy gate and a second dummy gate formed over said at least one fin;

wherein performing the fin cut comprises etching to remove an oxide layer between a first gate structure and a second gate structure, the first gate structure comprising the first dummy gate and a first gate patterning hard mask structure formed over the first dummy gate, the second gate structure comprising the second dummy gate and a second gate patterning hard mask structure formed over the second dummy gate; and

wherein performing the fin cut further comprises performing a directional nitride etch:

to remove a portion of the first gate patterning hard mask structure left exposed by the fin cut mask, the portion of the first gate patterning hard mask comprising a portion of a first sacrificial layer in the first gate patterning hard mask structure;

to remove a portion of the second gate patterning hard mask structure left exposed by the fin cut mask, the portion of the second gate patterning hard mask comprising a portion of a second sacrificial layer in the second gate patterning hard mask structure;

to remove portions of first spacers formed on sidewalls of the first gate structure and the second gate structure; and

to remove portions of second spacers formed on sidewalls of the first spacers and over an epitaxial layer formed over said at least one fin between the first gate structure and the second gate structure;

removing the fin cut mask; and

depositing an oxide to replace the portion of said at least one fin removed during the fin cut.

2. The method of claim 1 , wherein the fin cut mask covers at least a portion of a first gate structure comprising the first dummy gate and at least a portion of a second gate structure comprising the second dummy gate, and wherein the fin cut mask exposes an area between the first gate structure and the second gate structure.

3. The method of claim 1 , wherein the fin cut mask covers all of a first gate structure comprising the first dummy gate and all of a second gate structure comprising the second dummy gate, and wherein the fin cut mask exposes an area between the first gate structure and the second gate structure.

4. The method of claim 1 , wherein the fin cut mask exposes a first gate structure comprising the first dummy gate, a second gate structure comprising the second dummy gate, and an area between the first gate structure and the second gate structure.

5. The method of claim 1 , wherein the first dummy gate and the second dummy gate are retained following the fin cut.

6. The method of claim 1 , wherein the first dummy gate and the second dummy gate are removed during the fin cut, and wherein portions of a first gate patterning stack formed over the first dummy gate and portions of a second gate patterning stack formed over the second dummy gate are retained following the fin cut.

7. The method of claim 1 , wherein performing the fin cut further comprises performing an epitaxial and silicon etch to remove the epitaxial layer and the portion of said at least one fin between the first gate structure and the second gate structure.

8. The method of claim 7 , wherein the removed portion of said at least one fin comprises portions of said at least one fin not covered by the first spacers on sidewalls of the first gate structure and the second gate structure.

9. A method of forming a semiconductor structure, comprising:

forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure, the finFET structure comprising one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure;

performing a fin cut by removing a portion of at least one of the fins, the portion of said at least one fin being determined by an exposed area of the fin cut mask, the exposed area of the fin cut mask comprising at least a portion of said at least one fin between a first dummy gate and a second dummy gate formed over said at least one fin;

wherein performing the fin cut comprises etching to remove an oxide layer between a first gate structure and a second gate structure, the first gate structure comprising the first dummy gate and a first gate patterning hard mask structure formed over the first dummy gate, the second gate structure comprising the second dummy gate and a second gate patterning hard mask structure formed over the second dummy gate; and

wherein performing the fin cut comprises performing a directional nitride etch:

to remove a portion of the first gate patterning hard mask structure left exposed by the fin cut mask, the portion of the first gate patterning hard mask comprising all of a first sacrificial layer in the first gate patterning hard mask structure left exposed by the fin cut mask;

to remove a portion of the second gate patterning hard mask structure left exposed by the fin cut mask, the portion of the second gate patterning hard mask comprising all of a second sacrificial layer in the second gate patterning hard mask structure left exposed by the fin cut mask;

to remove portions of first spacers formed on sidewalls of the first gate structure and the second gate structure; and

to remove portions of second spacers formed on sidewalls of the first spacers and over an epitaxial layer formed over said at least one fin between the first gate structure and the second gate structure;

wherein the removed portions of the first spacers and the second spacers expose at least a portion of the first dummy gate and at least a portion of the second dummy gate;

removing the fin cut mask; and

depositing an oxide to replace the portion of said at least one fin removed during the fin cut.

10. The method of claim 9 , wherein performing the fin cut further comprises performing a nitride reactive-ion etching to remove the first spacers and the second spacers formed on sidewalls of the first gate structure and sidewalls of the second gate structure between the first dummy gate and the second dummy gate.

11. The method of claim 10 , wherein performing the fin cut further comprises performing a poly pull to remove the first dummy gate and the second dummy gate.

12. The method of claim 11 , wherein performing the fin cut further comprises performing an epitaxial and silicon etch to remove the epitaxial layer and the portion of said at least one fin between the remaining first spacers left exposed by removal of the first dummy gate and the second dummy gate.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0771 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0868 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051493/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2016
From: GREENE, ANDREW M.; GUO, DECHAO; RAMACHANDRAN, RAVIKUMAR; VENIGALLA, RAJASEKHAR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040029/0335 →
Continuity (1)
Related Publication 20180108655A1 · Apr 19, 2018