Resistive memory device having sidewall spacer electrode and method of making thereof
A resistive memory device includes a first electrode, a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode, a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode, and a second electrode containing the resistive memory cell.
1. A resistive memory device, comprising:
a first electrode;
a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode;
a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode; and
a second electrode containing the resistive memory cell, wherein:
the sidewall spacer electrode comprises a polycrystalline metallic material; and
a predominant portion of grain boundaries in a vertical portion of the polycrystalline metallic material are substantially horizontal.
2. The resistive memory device of claim 1 , wherein the sidewall spacer electrode is located on a sidewall of a dielectric pillar.
3. The resistive memory device of claim 2 , wherein the sidewall spacer electrode comprises a conductive tube which laterally surrounds the dielectric pillar.
4. The resistive memory device of claim 1 , wherein a predominant portion of the grain boundaries in the vertical portion of the polycrystalline metallic material extend along a direction within 15 degrees from a surface normal to a sidewall of the dielectric pillar.
5. The resistive memory device of claim 1 , wherein the polycrystalline metallic material comprises TiN, TaN or WN.
6. The resistive memory device of claim 2 , wherein:
the sidewall spacer electrode comprises one of a two-dimensional array of sidewall spacer electrodes located on respective sidewalls of a plurality of dielectric pillars;
the first electrode comprises one of a plurality of first electrically conductive lines, each contacting a respective row of sidewall spacer electrodes;
the resistive memory cell comprises one of a plurality of memory-material-containing lines; and
the second electrode comprises one of a plurality second electrically conductive lines, each of which contacts a respective memory-material-containing line.
7. The resistive memory device of claim 6 , wherein:
a first planar surface of each dielectric pillar contacts a respective first electrically conductive line;
a second planar surface of each dielectric pillar contacts a respective memory-material-containing line;
each sidewall spacer electrode within the two-dimensional array has an annular contact area with a respective memory-material-containing line; and
each sidewall spacer electrode within the two-dimensional array has another annular contact area with a respective first electrically conductive line.
8. The resistive memory device of claim 6 , wherein each memory-material-containing line has a same width as a respective second electrically conductive line in physical contact with the memory-material-containing line.
9. The resistive memory device of claim 1 , wherein the resistive memory material comprises a barrier modulated cell memory material portion.
10. The resistive memory device of claim 9 , wherein the resistive memory device further comprises a barrier material portion contacting the barrier modulated cell memory material portion.
11. The resistive memory device of claim 10 , wherein the barrier modulated cell memory material portion comprises a non-filamentary, electrically conductive metal oxide and the barrier material portion comprises an amorphous semiconductor material.
12. The resistive memory device of claim 11 , wherein:
the non-filamentary, electrically conductive metal oxide comprises sub-stoichiometric titanium oxide;
the amorphous semiconductor material is selected from silicon, germanium and silicon-germanium; and
a predominant portion of grain boundaries in a vertical portion of the sidewall spacer electrode extend along a direction within 15 degrees from horizontal plane located between the barrier material portion and the barrier modulated cell memory material portion.
13. The resistive memory device of claim 1 , further comprising:
a dielectric diffusion barrier layer contacting the first electrically conductive lines and all outer sidewalls of the two-dimensional array of sidewall spacer electrodes;
a first line level dielectric layer embedding the first electrically conductive lines;
a second line level dielectric layer embedding the second electrically conductive lines; and
a via level dielectric layer laterally surrounding each sidewall spacer electrode within the two-dimensional array of sidewall spacer electrodes.
14. A method of forming a resistive memory device, comprising:
forming a first electrode;
forming a dielectric pillar over the first electrode;
forming a continuous metallic material layer over the dielectric pillar;
removing an upper portion of the continuous metallic material layer located above the dielectric pillar to form a sidewall spacer electrode located on a sidewall of the dielectric pillar and in contact with the first electrode;
forming a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode; and
forming a second electrode containing the resistive memory cell, wherein:
the sidewall spacer electrode comprises a polycrystalline metallic material; and
a predominant portion of grain boundaries in a vertical portion of the polycrystalline metallic material are substantially horizontal.
15. The method of claim 14 , wherein the sidewall spacer electrode comprises a conductive tube which laterally surrounds the dielectric pillar.
16. The method of claim 14 , wherein:
a predominant portion of the grain boundaries in the vertical portion of the polycrystalline metallic material extend along a direction within 15 degrees from a surface normal to a sidewall of the dielectric pillar′ the polycrystalline metallic material comprises TiN, TaN or WN; and
the resistive memory material comprises a barrier modulated cell memory material portion.
17. The method of claim 16 , wherein:
the resistive memory device further comprises a barrier material portion contacting the barrier modulated cell memory material portion;
the barrier modulated cell memory material portion comprises a non-filamentary, electrically conductive metal oxide; and
the barrier material portion comprises an amorphous semiconductor material.
18. The method of claim 17 , wherein:
the non-filamentary, electrically conductive metal oxide comprises sub-stoichiometric titanium oxide;
the amorphous semiconductor material is selected from silicon, germanium and silicon-germanium; and
a predominant portion of grain boundaries in a vertical portion of the sidewall spacer electrode extend along a direction within 15 degrees from horizontal plane located between the barrier material portion and the barrier modulated cell memory material portion.
19. The method of claim 14 , wherein removing the upper portion of the continuous metallic material layer comprises anisotropically etching the continuous metallic material layer or performing a chemical mechanical planarization to remove the upper portion of the continuous metallic material layer.