IP Library Granted Patent US 10,192,967
Granted Patent B2
US 10,192,967 · App. 15/306,836 · Granted Jan 29, 2019

Silicon carbide semiconductor with trench gate

Inventors: Yu Saitoh (Osaka, JP); Tomoaki Hatayama (Osaka, JP); Takeyoshi Masuda (Osaka, JP)
Assignee: Sumitomo Electric Industries, Ltd.
H01L29/42368H01L21/02126H01L21/02236H01L21/02255H01L21/02332H01L21/049H01L21/0475H01L21/3065H01L21/3115H01L29/045H01L29/0657H01L29/1095H01L29/12H01L29/1608H01L29/4236H01L29/42376H01L29/66068H01L29/78H01L29/7813H01L21/0337H01L21/0485
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Quick Facts
Patent No.
US 10,192,967
App. No.
15/306,836
Granted
Jan 29, 2019
Kind
B2
Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion. A contact point between a first side surface portion and a second side surface portion is located in a third impurity region. An angle formed by the first side surface portion and a straight line extending through the contact point and parallel to the main surface is smaller than an angle formed by the second side surface portion and a boundary surface between a first impurity region and a second impurity region. A thickness of a portion of the gate oxide film on the contact point between the main surface and the first side surface portion is larger than a thickness of a portion of the gate oxide film on the second impurity region.

Claims (12)

1. A silicon carbide semiconductor device comprising:

a silicon carbide substrate having a main surface, the silicon carbide substrate including a first impurity region, a second impurity region, and a third impurity region, the first impurity region having first conductivity type, the second impurity region being provided on the first impurity region, the second impurity region having second conductivity type different from the first conductivity type, the third impurity region being provided on the second impurity region, the third impurity region having the first conductivity type, the third impurity region constituting at least a portion of the main surface, a trench being provided in the main surface to have a side surface and a bottom portion, the side surface extending to the first impurity region through the third impurity region and the second impurity region, the bottom portion being located in the first impurity region, the side surface including a first side surface portion and a second side surface portion, the first side surface portion being continuous to the main surface, the second side surface portion connecting the first side surface portion to the bottom portion, a contact point between the first side surface portion and the second side surface portion being located in the third impurity region, an angle formed by the first side surface portion and a straight line extending through the contact point between the first side surface portion and the second side surface portion and parallel to the main surface being smaller than an angle formed by the second side surface portion and a boundary surface between the first impurity region and the second impurity region;

a gate oxide film in contact with the third impurity region at the first side surface portion of the trench, in contact with the third impurity region and the second impurity region at the second side surface portion of the trench, and in contact with the first impurity region at the bottom portion of the trench; and

a gate electrode provided on the gate oxide film,

a thickness of a portion of the gate oxide film on a contact point between the main surface and the first side surface portion being larger than a thickness of a portion of the gate oxide film on the second impurity region,

wherein the first side surface portion is a first linear side surface portion, and the second side surface portion is a second linear side surface portion, and

wherein the width of the trench is increased from the bottom portion of the trench to the main surface in a tapered manner.

2. The silicon carbide semiconductor device according to claim 1 , wherein the angle formed by the second side surface portion and the boundary surface between the first impurity region and the second impurity region is not less than 50° and not more than 65°.

3. The silicon carbide semiconductor device according to claim 1 , wherein the angle formed by the first side surface portion and the straight line extending through the contact point between the first side surface portion and the second side surface portion and parallel to the main surface is not less than 20° and less than 50°.

4. The silicon carbide semiconductor device according to claim 1 , wherein a thickness of the portion of the gate oxide film on the bottom portion of the trench is larger than the thickness of the portion of the gate oxide film on the second impurity region.

5. The silicon carbide semiconductor device according to claim 1 , wherein the second side surface portion of the trench includes a first plane having a plane orientation of {0−33−8}.

6. The silicon carbide semiconductor device according to claim 5 , wherein the second side surface portion of the trench microscopically includes the first plane, and the second side surface portion microscopically further includes a second plane having a plane orientation of {0−11−1}.

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Jul 1, 2026
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUMI ELECTRIC CO., LTD.
Reel/Frame 075871/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2016
From: SAITOH, YU; HATAYAMA, TOMOAKI; MASUDA, TAKEYOSHI
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 040138/0634 →
Priority Claims (1)
JP 2014-104538 · May 20, 2014 · national
Continuity (1)
Related Publication 20170047415A1 · Feb 16, 2017