Array substrate, fabrication method, and corresponding display panel and electronic device

1. An array substrate, comprising: a base substrate, and a gate line, an insulating layer, a data line, a thin film transistor and a first active pad layer provided on the base substrate, wherein, the insulating layer is provided on the gate line, the data line is arranged on the gate line through the insulating layer and is arranged intersecting with the gate line, the first active pad layer is arranged on the gate line through the insulating layer and is arranged overlapping with the gate line, the first active pad layer and the gate line are separated by the insulating layer, the first active pad layer is arranged outside a region where the gate line and the data line overlap with each other, the thin film transistor comprises an active layer disposed on a side of the insulating layer away from the gate line and separated from the first active pad layer in a direction parallel to the base substrate, at least one of the first active pad layer and an edge of a part of the gate line where the gate line and the first active pad layer overlap with each other has a tip structure, wherein the tip structure comprises a serrated edge configured so that static electricity may be attracted to accumulate on the first active pad layer to increase the probability of electro static discharge.

2. The array substrate according to claim 1 , wherein a planar shape of the first active pad layer has an irregular shape.

3. The array substrate according to claim 1 , further comprising a data line pad layer and a pixel unit, wherein, the data line pad layer is provided on the first active pad layer and overlaps with the first active pad layer, the pixel unit is defined by the data line and the gate line crossing each other, the pixel unit comprises a pixel electrode, and the data line pad layer is not electrically connected with the pixel electrode horizontally.

4. The array substrate according to claim 3 , wherein the data line pad layer is electrically insulated from the data line.

5. The array substrate according to claim 3 , wherein the data line pad layer parallel to the base substrate has a serrate edge.

6. The array substrate according to claim 1 , further comprising a second active pad layer, wherein, the second active pad layer is provided between the insulating layer and the data line, and is located in a region where the gate line and the data line overlap with each other.

7. The array substrate according to claim 1 , further comprising at least one other first active pad layer, wherein the least one other first active pad layer is spaced apart from the first active pad layer in a direction parallel to the base substrate, and does not overlap with the first active pad layer in a direction perpendicular to the base substrate.

8. A display panel, comprising the array substrate according to claim 1 .

9. A fabrication method of an array substrate, the array substrate comprising a base substrate, and a gate line, an insulating layer, a data line, a thin film transistor and a first active pad layer provided on the base substrate, the fabrication method comprising: forming the gate line on the base substrate, forming the insulating layer on the gate line,

forming the thin film transistor on the insulating layer, arranging the data line on the gate line through the insulating layer and intersecting with the gate line, arranging the first active pad layer on the gate line through the insulating layer and overlapping with the gate line, wherein the first active pad layer and the gate line are separated by the insulating layer, and arranging the first active pad layer outside a region where the gate line and the data line overlap with each other, the thin film transistor comprises an active layer disposed on a side of the insulating layer away from the gate line and separated from the first active pad layer in a direction parallel to the base substrate, at least one of the first active pad layer and an edge of a part of the gate line where the gate line and the first active pad layer overlap with each other is formed to have a tip structure, wherein the tip structure comprises a serrated edge configured so that static electricity may be attracted to accumulate on the first active pad layer to increase the probability of electro static discharge.

10. The fabrication method of the array substrate according to claim 9 , wherein the first active pad layer is formed to have an irregular shape in a plan view.

11. The fabrication method of the array substrate according to claim 9 , further comprising forming a data line pad layer and a pixel unit, wherein, the data line pad layer is provided on the first active pad layer and overlaps with the first active pad layer, the pixel unit is defined by the data line and the gate line crossing each other, the pixel unit comprises a pixel electrode, and the data line pad layer is not electrically connected with the pixel electrode horizontally.

12. The fabrication method of the array substrate according to claim 11 , wherein the data line pad layer is formed to be electrically insulated from the data line.

13. The fabrication method of the array substrate according to claim 11 , wherein the data line pad layer is formed to have a serrate edge.

14. The fabrication method of the array substrate according to claim 9 , further comprising forming a second active pad layer, wherein, the second active pad layer is provided between the insulating layer and the data line, and is located in a region where the gate line and the data line overlap with each other.

15. The fabrication method of the array substrate according to claim 9 , further comprising forming at least one other first active pad layer, wherein the least one other first active pad layer is spaced apart from the first active pad layer in a direction parallel to the base substrate, and does not overlap with the first active pad layer in a direction perpendicular to the base substrate.

16. An electronic device, comprising the display panel according to claim 8 .