Supervisory memory management unit
A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU) translates the virtual address to a physical address of a memory with respect to the data processed by the CPU. A supervisory MMU translates the physical address of the first MMU to a storage address for storage and retrieval of the data in the memory. The supervisory MMU controls access to the memory via the storage address generated by the first MMU.
1. A computer system, comprising:
a central processing unit (CPU) to process a memory access request corresponding to a virtual address;
a first memory management unit (MMU) to:
determine a first mapping between the virtual address and a physical address of a physical address space of a memory device;
determine a first permission for accessing the memory device based on a physical address range associated with the first mapping; and
translate the virtual address to the physical address of-based on the first mapping; and
a supervisory MMU to:
determine a second mapping between the physical address and a storage address of a storage address space of the memory device;
determine a second permission for accessing the storage address for facilitating the memory access request; and
translate the physical address to the storage address based on the second mapping;
wherein the supervisory MMU controls access to the memory device via the storage address space, and
wherein the memory device includes a combination of volatile and non-volatile memory devices corresponding to the storage address space, and wherein the physical address space corresponds to the volatile memory device.
2. The computer system of claim 1 , wherein the first MMU is further to translate the virtual memory address to the physical address based on a first translation lookaside buffer (TLB) of the first MMU.
3. The computer system of claim 1 , wherein the supervisory MMU is further to translate the physical address to the storage address based on a second translation lookaside buffer (TLB) of the supervisory MMU.
4. The computer system of claim 1 , wherein the supervisory MMU determines the second permission from a storage page table storing the storage address.
5. The computer system of claim 1 , further comprising a supervisory fault handler to access a storage page table in the memory device in response to a supervisory page fault generated by the supervisory MMU.
6. The computer system of claim 5 , wherein the CPU is further to receive a notice of the supervisory page fault via a fault feedback path from the supervisory fault handler to the CPU.
7. The computer system of claim 6 , wherein the supervisory MMU and the CPU are to utilize a polled semaphore to coordinate fault operations in response to the supervisory fault.
8. The computer system of claim 1 , wherein the memory device is to store a memory page table accessible by the first MMU via a first memory access path from the first MMU, wherein the first memory access path is accessible in response to a TLB cache miss of the first MMU.
9. The computer system of claim 1 , wherein the memory device is to store a storage page table accessible via a second memory access path from the supervisory MMU or a third memory access path from a supervisory fault handler associated with the supervisory MMU.
10. The computer system of claim 1 , wherein a location indicated by the storage address is accessible via a fourth memory access path via the supervisory MMU, wherein the fourth memory access path facilitates an in-band read operation.
11. An apparatus, comprising:
a memory device comprising a combination of volatile and non-volatile memory devices corresponding to a storage address space;
a central processing unit (CPU) to process a memory access request corresponding to a virtual address;
a first memory management unit (MMU) to:
determine a first mapping between the virtual address and a physical address of a physical address space of the memory device;
determine a first permission for accessing the memory device based on a physical address range associated with the first mapping; and
translate the virtual address to the physical address ef-based on the first mapping; and
a supervisory MMU to:
determine a second mapping between the physical address and a storage address of the storage address space of the memory device;
determine a second permission for accessing the storage address for facilitating the memory access request; and
translate the physical address to the storage address based on the second mapping;
wherein the supervisory MMU controls access to the memory device via the storage address space, and
wherein the physical address space corresponds to the volatile memory device.
12. A method, comprising:
processing, by a central processing unit (CPU) of a computing device, a memory access request corresponding to a virtual address;
determining, by a first memory management unit (MMU) of the computing device, a first mapping of the virtual address and a physical address of a physical address space of a memory device;
determining, by the first MMU, a first permission for accessing the memory device based on a physical address range associated with the first mapping;
translating, by the first MMU, the virtual address to the physical address of-based on the first mapping;
determining, by a supervisory MMU of the computing device, a second mapping between the physical address and a storage address of a storage address space of the memory device;
determining, by the supervisory MMU, a second permission for accessing the storage address for facilitating the memory access request; and
translating, by the supervisory MMU, the physical address to the storage address based on the second mapping;
wherein the supervisory MMU controls access to the memory device via the storage address space,
wherein the memory device includes a combination of volatile and non-volatile memory devices corresponding to the storage address space, and wherein the physical address space corresponds to the volatile memory device.
13. The method of claim 12 , further comprising determining, by the supervisory MMU, the second permission from a storage page table storing the storage address.
14. The method of claim 12 , further comprising:
translating, by the first MMU, the virtual memory address to the physical address based on a first translation lookaside buffer (TLB) of the first MMU; and
translating, by the supervisory MMU, the physical address to the storage address based on a second translation lookaside buffer (TLB) of the supervisory MMU.
15. The method of claim 12 , further comprising accessing, by a supervisory fault handler of the computing device, a storage page table in the memory device in response to a supervisory page fault generated by the supervisory MMU.
16. The method of claim 15 , further comprising receiving, by the CPU, a notice of the supervisory page fault via a fault feedback path from the supervisory fault handler to the CPU.
17. The method of claim 16 , further comprising utilizing, by the supervisory MMU and the CPU, a polled semaphore to coordinate fault operations in response to the supervisory fault.
18. The method of claim 12 , further comprising storing, in the memory device, a memory page table accessible by the first MMU via a first memory access path from the first MMU, wherein the first memory access path is accessible in response to a TLB cache miss of the first MMU.
19. The method of claim 12 , further comprising storing, in the memory device, a storage page table accessible via a second memory access path from the supervisory MMU or a third memory access path from a supervisory fault handler associated with the supervisory MMU.
20. The method of claim 12 , wherein a location indicated by the storage address is accessible via a fourth memory access path via the supervisory MMU, wherein the fourth memory access path facilitates an in-band read operation.