Computer system for processing pixel data of an image
In an embodiment a computer system includes at least one master module configured to process data having a format of N bits, a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer and a memory management unit configured to control memory accesses of the at least one master module to the framebuffer, wherein the memory management unit is further configured to receive read memory access requests from the at least one master module, read at least one pixel in the framebuffer saved on P bits, and modify the format of the at least one read pixel by adding Q additional bits equal to a difference between N and P so as to format the at least one pixel on N bits before transmitting the at least one pixel to the at least one master module.
1 . A computer system comprising:
a first circuit configured to process data having a format of N bits, the first circuit comprising a central processor, a graphics processor, and a display;
a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer; and
a memory management circuit configured to control memory accesses of the first circuit to the framebuffer, wherein the memory management circuit is further configured to:
receive read memory access requests from the first circuit,
read a pixel in the framebuffer saved on P bits, and
modify the format of the pixel by adding Q additional bits equal to a difference between N and P to format the pixel on N bits before transmitting the pixel to the first circuit, wherein the Q additional bits comprise padding bits without color component information.
2 . The system according to claim 1 , wherein N is equal to thirty-two, P is equal to twenty-four, and wherein a value of each color component of each pixel is coded on eight bits so that Q is equal to eight.
3 . The system according to claim 1 , wherein each memory access request specifies a virtual address corresponding to a physical address to access the framebuffer.
4 . The system according to claim 3 , wherein the memory management circuit is configured to convert the virtual address into the corresponding physical address of the framebuffer.
5 . The system according to claim 1 , wherein the memory management circuit comprises a buffer configured to store the pixels received from the first circuit during a write access.
6 . The system according to claim 1 , wherein the memory management circuit comprises a cache memory configured to store the last read pixel in the framebuffer.
7 . A computer system comprising:
a first circuit configured to process data having N bits, the first circuit comprising a central processor, a graphics processor, and a display;
a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer; and
a memory management circuit configured to control memory accesses of the first circuit to the framebuffer, wherein the memory management circuit is further configured to:
receive write memory access requests from a pixel having a format on N bits including color component values of the pixel as well as Q additional bits equal to a difference between N and P, wherein the Q additional bits comprise padding bits without color component information,
modify the format of the pixel by deleting the Q additional bits to format the pixel on P bits before saving the pixel in the framebuffer, and
save the pixel in the framebuffer.
8 . The system according to claim 7 , wherein N is equal to thirty-two, P is equal to twenty-four, a value of each color component of each pixel being coded on eight bits so that Q is equal to eight.
9 . The system according to claim 7 , wherein each memory access request specifies a virtual address corresponding to a physical address to access the framebuffer.
10 . The system according to claim 9 , wherein the memory management circuit is configured to convert the virtual address into the corresponding physical address of the framebuffer.
11 . The system according to claim 7 , wherein the memory management circuit comprises at least one buffer configured to store the pixels received from the first circuit during a write access.
12 . A method for reading a pixel in a framebuffer based on a read access request emitted by a first circuit, wherein the first circuit is configured to process data having N bits, the first circuit comprising a central processor, a graphics processor, and a display, wherein the framebuffer is configured to store pixel color component values of an image and has a resolution of N bits, wherein each pixel is coded on P bits in the framebuffer, and wherein the pixels are stored one after another in the framebuffer, the method comprising:
receiving, by a memory management circuit, a read memory access request from the first circuit to the framebuffer;
reading, by the memory management circuit, the pixel in the framebuffer saved on P bits;
after reading, modifying, by the memory management circuit, a format of the at pixel by adding Q additional bits equal to a difference between N and P to format the pixel on N bits, wherein the Q additional bits comprise padding bits without color component information; and
after modifying, transmitting, by the memory management circuit, the pixel on N bits to the first circuit.
13 . The method according to claim 12 , wherein N is equal to thirty-two, P is equal to twenty-four, and wherein a value of each color component of each pixel is coded on eight bits so that Q is equal to eight.
14 . The method according to claim 12 , wherein each memory access request specifies a virtual address corresponding to a physical address to access the framebuffer.
15 . The method according to claim 14 , wherein reading comprises translating, by the memory management circuit, the virtual address specified in the memory access request into a physical address of the framebuffer.
16 . A method for writing a pixel in a framebuffer based on a write access request emitted by a first circuit, wherein the first circuit is configured to process data having N bits, the first circuit comprising a central processor, a graphics processor, and a display, wherein the framebuffer is configured to store pixel color component values of an image and has a resolution of N bits, wherein each pixel is coded on P bits in the framebuffer, and wherein the pixels are stored one after another in the framebuffer, the method comprising:
receiving, by a memory management circuit, a write memory access request from the first circuit to the framebuffer, the write access request specifying a pixel to write having a format on N bits including the color component values of the pixel on P bits as well as Q additional bits equal to a difference between N and P, wherein the Q additional bits comprise padding bits without color component information;
modifying, by the memory management circuit, the format of the pixel by deleting the Q additional bits to format the pixel on P bits; and
after modifying, saving, by the memory management circuit, the pixel on P bits in the framebuffer.
17 . The method according to claim 16 , wherein N is equal to thirty-two, P is equal to twenty-four, and wherein a value of each color component of each pixel is coded on eight bits so that Q is equal to eight.
18 . The method according to claim 16 , wherein each memory access request specifies a virtual address corresponding to a physical address to access the framebuffer.
19 . The method according to claim 18 , wherein reading comprises translating, by the memory management circuit, the virtual address specified in the memory access request into a physical address of the framebuffer.
20 . The method according to claim 16 , wherein the memory management circuit comprises an address channel configured to convert virtual addresses into physical addresses, a write channel configured to modify the format of pixels from N bits to P bits, and a read channel configured to modify the format of pixels from P bits to N bits.