AVD hardmask for damascene patterning
A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
1. An integrated circuit apparatus comprising:
an integrated circuit substrate comprising a contact point of a circuit device layer or an interconnection line;
a dielectric layer on the contact point, wherein the dielectric layer comprises a trench and a via wherein the trench has a length dimension and a width dimension and wherein the via extends from a base of the trench through the dielectric layer to the contact point and has a width dimension that is the same as the width dimension of the trench;
a hardmask on the dielectric layer, the hardmask comprising a dielectric material comprising a density greater than a density of a material of the dielectric layer; and
a conductive material in an opening of the hardmask and in the trench and the via.
2. The apparatus of claim 1 , wherein the dielectric layer comprises a material having a dielectric constant less than a dielectric constant of silicon dioxide and the dielectric material of the hardmask has a dielectric constant greater than a dielectric constant of silicon dioxide.
3. The apparatus of claim 2 , wherein the dielectric layer comprises a porous material.
4. The apparatus of claim 2 , wherein the dielectric material of the hardmask is selected from the group consisting of silicon oxynitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride and lanthanum oxide.
5. The apparatus of claim 1 , wherein the contact point comprises an interconnection line.
6. An integrated circuit apparatus comprising:
an integrated circuit substrate comprising a contact point of a circuit device or an interconnection line;
an interlayer dielectric material on the contact point, wherein the interlayer dielectric material comprises a trench and a via wherein the trench has a length dimension and a width dimension and wherein the via extends from a base of the trench through the interlayer dielectric material to the contact point and has a width dimension that is the same as the width dimension of the trench;
a second dielectric material on the interlayer dielectric material, the second dielectric material comprising a dielectric constant great than a dielectric constant of the interlayer dielectric material and the second dielectric material comprises a thickness that will not significantly effect an overall dielectric constant of the combination of the interlayer dielectric material and the second dielectric material; and
an interconnect material disposed through the second dielectric material and in the trench and the via.
7. The apparatus of claim 6 , wherein the interlayer dielectric material comprises a dielectric constant less than a dielectric constant of silicon dioxide and the second dielectric material comprises a dielectric constant greater than a dielectric constant of silicon dioxide.
8. The apparatus of claim 6 , wherein the interlayer dielectric layer comprises a porous material.
9. The apparatus of claim 6 , wherein the second dielectric material is selected from the group consisting of silicon oxynitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride and lanthanum oxide.
10. The apparatus of claim 6 , wherein the contact point comprises an interconnection line.
11. An integrated circuit structure, comprising:
a first interconnection line above a substrate;
an etch stop layer above the first interconnection line;
an interlayer dielectric (ILD) layer on the etch stop layer;
a conductive via in the ILD layer and through a portion of the etch stop layer, the conductive via on a portion of the interconnection line, wherein the conductive via has substantially vertical sidewalls spaced apart by a width along a first horizontal direction; and
a second interconnection line in the ILD layer and on the conductive via, the second interconnection line having substantially vertical sidewalls spaced apart by the width along the first horizontal direction, and the second interconnection line having a length along a second horizontal direction orthogonal to the first horizontal direction, wherein the substantially vertical sidewalls of the second interconnection line are continuous with the substantially vertical sidewalls of the conductive via.
12. The integrated circuit structure of claim 11 , further comprising:
a hardmask layer on the second interconnection line, the hardmask layer comprising a high k material.