Method of fabricating an electrical contact for use on a semiconductor device

1. A method of manufacturing a group III-V semiconductor device, the method comprising:

forming a gate contact that comprises an electrode stack including a first titanium layer, an aluminum layer over the first titanium layer, and a second titanium layer over the aluminum layer; and

forming a biased reactive capping layer over the second titanium layer, the biased reactive capping layer comprising biased reactive titanium nitride,

wherein the gate contact is a gate electrode that makes Schottky contact with the group III-V semiconductor device.

2. The method of claim 1 , wherein the aluminum layer of the electrode stack further comprises silicon.

3. The method of claim 1 , wherein the group III-V semiconductor device comprises a high electron mobility transistor (HEMT).

4. A method of manufacturing a group III-V semiconductor device, the method comprising:

forming a gate contact over a gate insulator layer so as to form a gate of the group III-V semiconductor device, the gate contact comprising an electrode stack including a first titanium layer, an aluminum layer over the first titanium layer, and a second titanium layer over the aluminum layer; and

forming a biased reactive capping layer over the second titanium layer, the biased reactive capping layer comprising biased reactive titanium nitride.

5. The method of claim 4 , wherein the aluminum layer of the electrode stack further comprises silicon.

6. The method of claim 4 , wherein the group III-V semiconductor device comprises a high electron mobility transistor (HEMT).

7. A method of fabricating an electrical contact for use on a semiconductor device, the method comprising:

forming an electrode stack including a plurality of metal layers over the semiconductor device;

depositing a refractory metal nitride capping layer for the electrode stack over the plurality of metal layers; and

forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.

8. The method of claim 7 , wherein depositing the refractory metal nitride capping layer comprises biasing a substrate supporting the semiconductor device while performing a deposition process in the presence of nitrogen gas so as to form a biased reactive refractory metal nitride capping layer over the plurality of metal layers.

9. The method of claim 7 , wherein depositing the refractory metal nitride capping layer comprises depositing a titanium nitride capping layer over the plurality of metal layers.

10. The method of claim 7 , wherein depositing the refractory metal nitride capping layer comprises depositing a tantalum nitride capping layer over the plurality of metal layers.

11. The method of claim 7 , wherein forming the electrode stack comprises:

forming a first metal layer comprising titanium;

forming a second metal layer comprising aluminum over the first metal layer; and

forming a third metal layer comprising titanium over the second metal layer.

12. The method of claim 7 , further comprising annealing the electrode stack at a temperature of approximately 850° C.

13. The method of claim 7 , wherein the semiconductor device is a group III-V semiconductor device.