Bending circuit for static random access memory (SRAM) self-timer
View Patent ↗The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.
1. A circuit, comprising:
a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter, and a source connected to ground;
a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter;
a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter; and
a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.
2. The circuit of claim 1 , wherein the input of the inverter is coupled to an input node through an input circuit.
3. The circuit of claim 2 , wherein the input circuit further comprises:
a fifth transistor with a source connected to a voltage power supply and a gate connected to the input node;
a sixth transistor with a drain connected to a drain of the fifth transistor and a gate connected to the voltage power supply; and
a seventh transistor with a drain connected to a source of the sixth transistor, a gate connected to the input node, and a source connected to ground.
4. The circuit of claim 3 , wherein the fifth transistor is a PFET transistor and the sixth transistor and the seventh transistor are NFET transistors.
5. The circuit of claim 1 , wherein the capacitor comprises a transistor in which the gate is connected to the drain of the second transistor and the source of the transistor is connected to the drain of the transistor.
6. The circuit of claim 5 , wherein the transistor is a NFET transistor.
7. The circuit of claim 1 , wherein the inverter comprises at least two transistors.
8. The circuit of claim 7 , wherein the at least two transistors comprises a PFET transistor and a NFET transistor.
9. The circuit of claim 1 , wherein the first transistor is a NFET transistor.
10. The circuit of claim 1 , wherein the second transistor, the third transistor, and the fourth transistor are PFET transistors.
11. The circuit of claim 1 , wherein the circuit comprises a static random access memory (SRAM) circuit.
12. The circuit of claim 1 , wherein when the input of the inverter goes low, the capacitor is charged, the fourth transistor will turn on, and the output node transitions from low to high.
13. The circuit of claim 1 , further comprising a voltage power supply input to the circuit, and at a low voltage value of the voltage power supply input, a self-timer delay of the circuit is increased.
14. The circuit of claim 13 , wherein at a high voltage value of the voltage power supply input, a self-timer delay of the circuit is at a stable value.
15. A bending circuit of a memory circuit, comprising:
a first NFET transistor with a drain connected to a capacitor, a gate connected to an input of an inverter, and a source connected to ground;
a first PFET transistor with a drain connected to the capacitor and a gate connected to the input of the inverter;
a second PFET transistor with a source connected to an output of the inverter, a drain connected to a source of the first PFET transistor, and a gate connected to the input of the inverter;
a third PFET transistor with a source connected to the source of the second PFET transistor, a drain connected to ground, and a gate connected to the capacitor,
wherein the input of the inverter is coupled to an input node through an input circuit.
16. The bending circuit of claim 15 , wherein when the input of the inverter goes low, the capacitor is charged, the third PFET transistor will turn on, and the output node transitions from low to high.
17. The bending circuit of claim 15 , further comprising a voltage power supply input to the input circuit, and at a low voltage value of the voltage power supply input, a self-timer delay of the memory circuit is increased.