Fan-out semiconductor package and method of manufacturing same

1. A fan-out semiconductor package, comprising:

an insulating layer and conductive patterns disposed on a first side of the insulating layer;

a frame having a through hole and disposed on a second side of the insulating layer opposing the first side;

a metal layer having a hole, and having upper and lower surfaces being in physical contact with a lower surface of the frame and the second side of the insulating layer, respectively;

a semiconductor chip having first and second surfaces opposing each other, including electrode pads disposed on the first surface and facing the second side of the insulating layer, and disposed on a portion of the insulating layer and within the through hole of the frame and the hole of the metal layer, the electrode pads being electrically connected to the conductive patterns through vias penetrating through the insulating layer; and

an encapsulant extending continuously to cover an upper surface of the frame and the second surface of the semiconductor chip, to fill at least a portion of the through hole, and to cover a side surface of the metal layer connecting the upper and lower surfaces of the metal layer,

wherein the metal layer is electrically insulated from the semiconductor chip.

2. The fan-out semiconductor package of claim 1 , wherein the metal layer is conterminous with the lower surface of the frame.

3. The fan-out semiconductor package of claim 1 , wherein the metal layer has a width narrower than a width of the frame.

4. The fan-out semiconductor package of claim 1 , wherein lower surfaces of the electrode pads and the lower surface of the metal layer are positioned on the same level.

5. The fan-out semiconductor package of claim 1 , wherein the metal layer comprises a plurality of holes formed therein.

6. The fan-out semiconductor package of claim 5 , wherein the plurality of holes form a grid.

7. The fan-out semiconductor package of claim 1 , wherein the frame comprises a conductive via passing through the frame to be electrically connected to one of the conductive patterns.

8. The fan-out semiconductor package of claim 7 , further comprising another metal layer spaced apart from the metal layer, surrounded by the metal layer, and disposed on the same level as the metal layer,

wherein the conductive via is electrically connected to the one of the conductive patterns through the another metal layer.

9. The fan-out semiconductor package of claim 1 , wherein the metal layer has a plurality of regions space apart from each other.

10. The fan-out semiconductor package of claim 1 , further comprising a conductive via passing through the encapsulant to be electrically connected to one of the conductive patterns.

11. A fan-out semiconductor package comprising:

a redistribution layer;

a frame having a through hole, the frame disposed on the redistribution layer;

a metal layer disposed between the redistribution layer and the frame, having a hole, and coupled to the frame to protect the frame; and

a semiconductor chip disposed on a portion of the redistribution layer within the through hole of the frame and the hole of the metal layer, and electrically connected to the redistribution layer,

wherein the metal layer is electrically insulated from the semiconductor chip,

the metal layer is attached to a lower surface of the frame defining a frame, and has a shape corresponding to a shape of the lower surface of the frame, and

the metal layer is disposed on the lower surface of the frame, and no metal layer is disposed on an upper surface of the frame opposing the lower surface.

12. A fan-out semiconductor package, comprising:

a lower layer comprising connection terminals;

an upper layer comprising an encapsulant, a frame disposed on a metal layer and having a lower surface facing the metal layer, and a semiconductor chip disposed in a through hole of the frame and having electrode pads facing the lower layer and disposed on a lower surface of the semiconductor chip; and

a middle layer defining a redistribution layer disposed contiguously between the upper layer and the lower layer,

wherein the metal layer is electrically insulated from the semiconductor chip, and

the encapsulant extends continuously to cover an upper surface of the semiconductor chip opposing the lower surface of the semiconductor chip and an upper surface of the frame opposing the lower surface of the frame, to fill a portion of the through hole, and to cover a side surface of the metal layer.

13. The fan-out semiconductor package of claim 12 , further comprising a conductive via penetrating through the encapsulant and the frame to electrically connect to the middle layer.

14. The fan-out semiconductor package of claim 12 , wherein the fan-out semiconductor package is a fan-out wafer level package (WLP).

15. An electronic device, comprising the fan-out semiconductor package of claim 12 .