Systems, methods and devices for programming a multilevel resistive memory cell

1. A method of programming a memory device, comprising:

applying one or more forward-biased electrical pulses to a memory cell; and

programming the memory cell from an intermediate programming state to a set programming state based at least in part on applying the one or more forward-biased electrical pulses, wherein the one or more forward-biased electrical pulses ramp in a first sequence.

2. The method of claim 1 , further comprising:

applying one or more reverse-biased electrical pulses to the memory cell; and

programming the memory cell from the set programming state to the intermediate programming state based at least in part on applying the one or more reverse-biased electrical pulses, wherein the one or more reverse-biased electrical pulses ramp in a second sequence different from the first sequence.

3. The method of claim 2 , wherein the first sequence comprises a falling staircase sequence, wherein the second sequence comprises a rising staircase sequence, and wherein the one or more forward-biased electrical pulses, the one or more reverse-biased electrical pulses, or both ramp sequentially.

4. The method of claim 2 , further comprising:

modulating a trailing edge of at least some of the one or more reverse-biased electrical pulses,

wherein programming the memory cell from the set programming state to the intermediate programming state is based at least in part on the modulating.

5. The method of claim 1 , further comprising:

modulating a trailing edge of at least some of the one or more forward-biased electrical pulses,

wherein programming the memory cell from the intermediate programming state to the set programming state is based at least in part on the modulating.

6. The method of claim 1 , further comprising:

applying one or more reverse-biased electrical pulses to the memory cell; and

programming the memory cell from the set programming state to a reset programming state based at least in part on applying the one or more reverse-biased electrical pulses, wherein the one or more reverse-biased electrical pulses sequentially ramp in a rising staircase sequence.

7. The method of claim 6 , further comprising:

programming the memory cell from the reset programming state to the set programming state based at least in part on applying the one or more forward-biased electrical pulses, wherein the one or more forward-biased electrical pulses sequentially ramp in a falling staircase sequence.

8. The method of claim 7 , wherein the memory cell comprises a phase change material, wherein the set programming state comprises a crystalline state having a first threshold voltage characteristic, and wherein the reset programming state comprises an amorphous state having a second threshold voltage characteristic.

9. The method of claim 1 , further comprising:

programming the memory cell from the set programming state to a reset programming state based at least in part on applying the one or more forward-biased electrical pulses, wherein the one or more forward-biased electrical pulses sequentially ramp in a rising staircase sequence.

10. The method of claim 1 , wherein applying the one or more forward-biased electrical pulses comprises:

applying a voltage across a storage component such that a current flows from a top electrode to a bottom electrode of the storage component.

11. A memory device, comprising:

a memory array comprising a plurality of memory cells; and

a control unit configured to program one or more memory cells of the plurality of memory cells from an intermediate programming state to a set programming state based at least in part on applying one or more forward-biased electrical pulses that ramp in a first sequence to the one or more memory cells.

12. The memory device of claim 11 , the control unit configured to:

program the one or more memory cells from the set programming state to the intermediate programming state based at least in part on applying one or more reverse-biased electrical pulses that sequentially ramp in a second sequence to the one or more memory cells.

13. The memory device of claim 11 , the control unit configured to:

program the one or more memory cells from the set programming state to a reset programming state based at least in part on applying one or more reverse-biased electrical pulses that ramp in a second sequence to the one or more memory cells.

14. The memory device of claim 13 , wherein the first sequence comprises a decreasing sequence and the second sequence comprises an increasing sequence, and wherein the one or more forward-biased electrical pulses and the one or more reverse-biased electrical pulses ramp sequentially.

15. The memory device of claim 11 , the control unit configured to:

program the one or more memory cells from the set programming state to a reset programming state based at least in part on applying the one or more forward-biased electrical pulses that sequentially ramp in an increasing sequence to the one or more memory cells.

16. The memory device of claim 15 , wherein the one or more memory cells comprise a phase change material, wherein the set programming state comprises a crystalline state having a first threshold voltage characteristic, and wherein the reset programming state comprises an amorphous state having a second threshold voltage characteristic.

17. A system, comprising:

a processor; and

a memory device comprising a plurality of memory cells, the memory device communicatively coupled to the processor and configured to:

program one or more memory cells of the plurality of memory cells from an intermediate programming state to a set programming state based at least in part on applying one or more forward-biased electrical pulses that ramp in a first sequence to the one or more memory cells.

18. The system of claim 17 , the memory device configured to:

program the one or more memory cells to the intermediate programming state, a reset programming state, or both based at least in part on applying one or more reverse-biased electrical pulses to the one or more memory cells.

19. The system of claim 18 , wherein the one or more reverse-biased electrical pulses ramp in the first sequence, and wherein the one or more forward-biased electrical pulses ramp in a second sequence different from the first sequence.

20. The system of claim 19 , wherein the one or more memory cells comprise a phase change material, wherein the set programming state comprises a crystalline state having a first threshold voltage characteristic, and wherein the reset programming state comprises an amorphous state having a second threshold voltage characteristic.