Distributed current source/sink using inactive memory elements
A Multi-Time-Programmable-Memory (MTPM) array architecture, whose structure comprising of having Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) memory elements arranged in a set of twin-pairs coupled by wordlines (WLs), bitlines (BLs) and sourcelines (SLs). More specifically, the use of inactive portions of the MTPM array structure as substitutes for conventional BL write driver areas by utilizing a set of twin-pairs acting in parallel. These substituted twin-pair sets will improve programming efficiency (VGS) and retention (VDS) through a lowering Interconnect (IR) drop and VDS drops at the BL write driver.
1. A Multi-Time Programmable Memory (MTPM) device comprising:
a first pair of twin-cell Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) gate-coupled to a first wordline and a second pair of twin-cell MOSFETs gate-coupled to a second wordline;
a true bitline drain-coupled to a first MOSFET in the first pair and source-coupled to a first MOSFET in the second pair;
a complementary bitline drain-coupled to a second MOSFET in the second pair and source-coupled to a second MOSFET in the first pair;
a first sourceline source-coupled to the first MOSFET in the first pair;
a second sourceline drain-coupled to the first MOSFET in the second pair and source-coupled to the second MOSFET in the second pair; and
a third sourceline drain-coupled to the second MOSFET in the first pair.
2. The MTPM device of claim 1 , wherein the MTPM device performs a programming operation for the first MOSFET in the first twin-cell pair, in response to:
a first predetermined voltage being applied to the first wordline, a second predetermined voltage being applied to the second wordline, a third predetermined voltage being applied to the first sourceline;
the second sourceline being set to ground; and
the third sourceline, the true bitline and the complementary bitline being set to float.
3. The MTPM device of claim 2 , wherein the first predetermined voltage is about 2V, the second predetermined voltage is about 0.8V, and the third predetermined voltage is about 1.5V.
4. The MTPM device of claim 1 , wherein the MTPM device performs a read operation in response to:
a first predetermined voltage being applied to the first wordline;
the second wordline, the first sourceline and the third sourceline being set to ground;
the second sourceline being set to float; and
the true bitline and the complementary bitline operating in sense.
5. The MTPM device of claim 4 , wherein the first predetermined voltage is about 0.5V.
6. The MTPM device of claim 1 , wherein the MTPM device performs an erase operation in response to:
setting the first wordline and the second wordline to ground;
setting the first sourceline, the second sourceline and the third sourceline to float; and
applying a set voltage to the true bitline and the complementary bitline.
7. The MTPM device of claim 1 , wherein an inactive portion of the MTPM array is reused to distribute the BL current during programming, thereby mimicking a BL driver functionality, and reducing the BL wire drop.
8. A Multi-Time Programmable Memory (MTPM) device comprising:
a first pair of twin-cell MOSFETs coupled to a first sourceline, wherein the first sourceline is source-coupled to a first MOSFET in the first pair and is further drain-coupled to a second MOSFET in the first pair;
a second pair of twin-cell MOSFETs coupled to a second sourceline, wherein the second sourceline is drain-coupled to a first MOSFET in the second pair and is further source-coupled to a second MOSFET in the second pair;
a first wordline gate-coupled to the first MOSFET in the first pair;
a second wordline gate-coupled to the first MOSFET in the second pair;
a third wordline gate-coupled to the second MOSFET in the second pair;
a fourth wordline gate-coupled to the second MOSFET in the first pair;
a true bitline drain-coupled to the first MOSFET in the first pair and source-coupled to the first MOSFET in the second pair, wherein the true bitline is set to float; and
a complementary bitline drain-coupled to the second MOSFET in the second pair and source-coupled to the second MOSFET in the first pair, wherein the complementary bitline is set to float.
9. The MTPM device of claim 8 , wherein:
the first wordline is gate-coupled to only the first MOSFET in the first pair;
the second wordline gate-coupled to only the first MOSFET in the second pair;
the third wordline gate-coupled to only the second MOSFET in the second pair;
the fourth wordline gate-coupled to only the second MOSFET in the first pair.
10. The MTPM device of claim 8 , wherein the MTPM device performs a programming operation for the first MOSFET in the first twin-cell pair, in response to:
a first predetermined voltage being applied to the first wordline and the fourth wordline, a second predetermined voltage being applied to the second wordline, the third wordline set to ground, a third predetermined voltage on the first sourceline, and the second sourceline set to ground; and
the true bitline and the complementary bitline being set to float.
11. The MTPM device of claim 10 , wherein the first predetermined voltage is about 2V, the second predetermined voltage is about 0.8V, and the third predetermined voltage is about 1.5V.
12. The MTPM device of claim 8 , wherein the MTPM device performs an erase operation in response to:
the first wordline, the second wordline, the third wordline and the fourth wordline being set to ground;
setting the first sourceline and the second sourceline to float; and
applying a set voltage to the true bitline and the complementary bitline.
13. The MTPM device of claim 8 , wherein an inactive portion of the MTPM array is reused to distribute the BL current during programming, thereby mimicking a BL driver functionality, and reducing the BL wire drop.
14. A MTPM Matrix array comprising of an array of paired twin-cell devices, each paired twin-cell device comprising:
a first pair of twin-cell Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) gate-coupled to a first wordline and a second pair of twin-cell MOSFETs gate-coupled to a second wordline;
a true bitline drain-coupled to a first MOSFET in the first pair and source-coupled to a first MOSFET in the second pair;
a complementary bitline drain-coupled to a second MOSFET in the second pair and source-coupled to a second MOSFET in the first pair;
a first sourceline source-coupled to the first MOSFET in the first pair;
a second sourceline drain-coupled to the first MOSFET in the second pair and source-coupled to the second MOSFET in the second pair; and
a third sourceline drain-coupled to the second MOSFET in the first pair.
15. The MTPM Matrix array of claim 14 , wherein the MPTPM Matix array performs a programming operation for the first MOSFET in the first twin-cell pair, in response to:
a first predetermined voltage being applied to the first wordline, a second predetermined voltage being applied to the second wordline, a third predetermined voltage being applied to the first sourceline;
the second sourceline being set to ground; and
the third sourceline, the true bitline and the complementary bitline being set to float.
16. The MTPM Matrix array of claim 15 , wherein the first predetermined voltage is about 2V, the second predetermined voltage is about 0.8V, and the third predetermined voltage is about 1.5V.
17. The MTPM Matrix array of claim 14 , wherein the MTPM device performs a read operation in response to:
a first predetermined voltage being applied to the first wordline;
the second wordline, the first sourceline and the third sourceline being set to ground;
the second sourceline being set to float; and
the true bitline and the complementary bitline operating in sense.
18. The MTPM Matrix array of claim 17 , wherein the first predetermined voltage is about 0.5V.
19. The MTPM Matrix array of claim 14 , wherein the MTPM device performs an erase operation in response to:
setting the first wordline and the second wordline to ground;
setting the first sourceline, the second sourceline and the third sourceline to float; and
applying a set voltage to the true bitline and the complementary bitline.
20. The MTPM Matrix of claim 14 , wherein an inactive portion of the MTPM array is reused to distribute the BL current during programming, thereby mimicking a BL driver functionality, and reducing the BL wire drop.