IP Library Granted Patent US 9,929,020
Granted Patent B2
US 9,929,020 · App. 15/363,596 · Granted Mar 27, 2018

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

Inventors: Cheng Chi (Jersey City, NJ); Fee Li Lie (Albany, NY); Chi-Chun Liu (Altamont, NY); Ruilong Xie (Albany, NY)
Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION; GLOBALFOUNDRIES INC.
H01L21/3086H01L21/3081H01L21/31144H01L21/823431
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,929,020
App. No.
15/363,596
Granted
Mar 27, 2018
Kind
B2
Abstract

A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Claims (40)

1. A method of making a semiconductor device, the method comprising:

disposing a hard mask stack on a substrate, the hard mask stack comprising a first hard mask layer in contact with the substrate, an amorphous silicon layer on the first hard mask layer, and a second hard mask layer on the amorphous silicon layer;

disposing an oxide layer and a neutral layer on the second hard mask layer;

removing a portion of the oxide layer and the neutral layer to expose a portion of the second hard mask layer;

forming a guiding pattern by selectively backfilling a polymeric material in the exposed portion of the second hard mask layer;

forming a self-assembled block copolymer layer on the guiding pattern, the guiding pattern comprising the neutral layer and the polymeric material that is backfilled;

removing a portion of the block copolymer layer to form an etch template with the polymeric material that is remaining;

etching the neutral layer, the oxide layer, the second hard mask layer, the amorphous silicon layer, and the first hard mask layer to transfer a pattern from the etch template into the neutral layer, the oxide layer, the second hard mask layer, the amorphous silicon layer, and the first hard mask layer;

etching the substrate to transfer the pattern from the hard mask stack into the substrate and form a first fin comprising a first portion of the first hard mask layer disposed on the first fin and a second fin comprising a second portion of the first hard mask layer disposed on the second fin, the second portion being thicker than the first portion;

replacing the second portion of the first hard mask layer on the second fin with a third hard mask material; and

etching to remove the first fin.

2. The method of claim 1 , wherein the second fin further comprises a portion of the amorphous silicon layer on the second portion of the first hard mask layer.

3. The method of claim 2 , wherein the portion of the amorphous silicon layer is replaced with the third hard mask material.

4. The method of claim 1 , wherein the first hard mask layer comprises silicon nitride.

5. The method of claim 4 , wherein the second hard mask layer comprises silicon nitride.

6. The method of claim 1 , wherein replacing the second portion of the first hard mask layer comprises a selective etch process.

7. The method of claim 1 , wherein the first hard mask layer is different than the third hard mask material.

8. The method of claim 1 , wherein the third hard mask material is SiBCN, SiBN, SiCN, or a combination thereof.

9. The method of claim 1 , wherein the substrate comprises silicon, germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or any combination thereof.

10. The method of claim 1 , wherein etching to remove the first fin is a selective etch process that selectively removes material of the first fin.

11. A method of making a semiconductor device, the method comprising:

disposing a hard mask stack on a substrate, the hard mask stack comprising a first hard mask layer in contact with the substrate, an amorphous silicon layer on the first hard mask layer, and a second hard mask layer on the amorphous silicon layer;

disposing an oxide layer and a neutral layer on the second hard mask layer;

removing a portion of the oxide layer and the neutral layer to expose a portion of the second hard mask layer;

forming a guiding pattern by selectively backfilling a polymeric material in the exposed portion of the second hard mask layer;

forming a self-assembled block copolymer layer on the guiding pattern, the guiding pattern comprising the neutral layer and the polymeric material that is backfilled, the self-assembled block copolymer layer comprising polystyrene (PS) and poly methyl methacrylate (PMMA);

removing a portion of the block copolymer layer to form an etch template with the polymeric material that is remaining;

etching the neutral layer, the oxide layer, the second hard mask layer, the amorphous silicon layer, and the first hard mask layer to transfer a pattern from the etch template into the neutral layer, the oxide layer, the second hard mask layer, the amorphous silicon layer, and the first hard mask layer;

etching the substrate to transfer the pattern from the hard mask stack into the substrate and form a first fin comprising a first portion of the first hard mask layer disposed on the first fin and a second fin comprising a second portion of the first hard mask layer disposed on the second fin, the second portion being thicker than the first portion;

replacing the second portion of the first hard mask layer on the second fin with a third hard mask material; and

etching to remove the first fin.

12. The method of claim 11 , wherein the second fin further comprises a portion of the amorphous silicon layer on the second portion of the first hard mask layer.

13. The method of claim 12 , wherein the portion of the amorphous silicon layer is replaced with the third hard mask material.

14. The method of claim 11 , wherein the first hard mask layer comprises silicon nitride.

15. The method of claim 14 , wherein the second hard mask layer comprises silicon nitride.

16. The method of claim 11 , wherein replacing the second portion of the first hard mask layer comprises a selective etch process.

17. The method of claim 11 , wherein the first hard mask layer is different than the third hard mask material.

18. The method of claim 11 , wherein the third hard mask material is SiBCN, SiBN, SiCN, or a combination thereof.

19. The method of claim 11 , wherein the substrate comprises silicon, germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or any combination thereof.

20. The method of claim 11 , wherein etching to remove the first fin is a selective etch process that selectively removes material of the first fin.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2016
From: CHI, CHENG; LIE, FEE LI; LIU, CHI-CHUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040454/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2016
From: XIE, RUILONG
To: GLOBALFOUNDRIES, INC.
Reel/Frame 040454/0904 →
Continuity (2)
Division 14870932 · Sep 30, 2015
Related Publication 20170092507A1 · Mar 30, 2017