Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip and including redistribution layers electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member and having openings exposing at least portions of the redistribution layer of the second interconnection member; and an under-bump metal layer disposed on the passivation layer and filling at least portions of the openings. In the under-bump metal layer, the number of conductor layers formed on a surface of the passivation layer is different from that of conductor layers formed on the exposed redistribution layer and walls of the openings.
1. A semiconductor package comprising:
a first interconnection member including a redistribution layer;
a semiconductor chip disposed on the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, the connection pads of the semiconductor chip being electrically connected to the redistribution layer of the first interconnection member;
an encapsulant encapsulating the inactive surface of the semiconductor chip;
a passivation layer including an inner surface in contact with the first interconnection member and an outer surface opposing the inner surface, and having an opening exposing a portion of the redistribution layer of the first interconnection member; and
an under-bump metal layer disposed on the passivation layer and filling at least a portion of the opening,
wherein the under-bump metal layer includes a first conductor layer disposed only on the outer surface of the passivation layer.
2. The semiconductor package of claim 1 , wherein the number of conductor layers formed on the outer surface of the passivation layer is larger than the number of conductor layers formed on the exposed redistribution layer and a wall of the opening.
3. The semiconductor package of claim 1 , wherein the under-bump metal layer further includes a second conductor layer disposed on the first conductor layer and extending to contact a wall of the opening and the exposed redistribution layer, and a third conductor layer formed on the second conductor layer.
4. The semiconductor package of claim 3 , wherein the first conductor layer includes electrolytic copper (Cu), the second conductor layer includes electroless copper (Cu), and the third conductor layer includes electrolytic copper (Cu).
5. The semiconductor package of claim 3 , wherein the second conductor layer has a thickness less than thicknesses of the first conductor layer and the third conductor layer.
6. The semiconductor package of claim 3 , wherein the passivation layer includes an inorganic filler and an insulating resin.
7. The semiconductor package of claim 6 , wherein at least one of chemical reaction groups included in the insulating resin of the passivation layer is self-assembled to a metal of the first conductor layer.
8. The semiconductor package of claim 1 , further comprising connection terminals disposed on the under-bump metal layer and electrically connected to the connection pads of the semiconductor chip,
wherein at least one of the connection terminals is disposed in a fan-out region.
9. The semiconductor package of claim 1 , further comprising a second interconnection member having a through-hole in which the semiconductor chip is disposed,
wherein the encapsulant encapsulates a portion of the second interconnection member,
the second interconnection member includes a first insulating layer, a first redistribution layer in contact with the first interconnection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and
the first and second redistribution layers are electrically connected to the connection pads.
10. The semiconductor package of claim 9 , wherein the second interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
the third redistribution layer is electrically connected to the connection pads.
11. The semiconductor package of claim 9 , wherein a distance between the redistribution layer of the first interconnection member and the first redistribution layer is greater than that between the redistribution layer of the first interconnection member and the connection pads.
12. The semiconductor package of claim 9 , wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the first interconnection member.
13. The semiconductor package of claim 9 , wherein a lower surface of the first redistribution layer is disposed on a level above a lower surface of the connection pads.
14. The semiconductor package of claim 10 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.
15. The semiconductor package of claim 1 , further comprising a second interconnection member having a through-hole in which the semiconductor chip is disposed,
wherein the encapsulant encapsulates a portion of the second interconnection member,
the second interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
the first to third redistribution layers are electrically connected to the connection pads.
16. The semiconductor package of claim 15 , wherein the second interconnection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
the fourth redistribution layer is electrically connected to the connection pads.
17. The semiconductor package of claim 15 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.
18. The semiconductor package of claim 15 , wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the first interconnection member.
19. The semiconductor package of claim 15 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.
20. The semiconductor package of claim 15 , wherein a lower surface of the third redistribution layer is disposed on a level below a lower surface of the connection pads.
21. The semiconductor package of claim 1 , further comprising a rigid member having a through-hole in which the semiconductor chip is disposed,
wherein the encapsulant encapsulates a portion of the rigid member.
22. The semiconductor package of claim 1 , further comprising a second interconnection member having a through-hole in which the semiconductor chip is disposed,
wherein the encapsulant encapsulates a portion of the second interconnection member, the second interconnection member includes a first insulating layer, and a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, and
the first and second redistribution layers are electrically connected to the connection pads.