Digitally controlled varactor structure for high resolution DCO
A digitally controlled varactor device comprising: a set of bulk nMOS field effect transistors bulk tied to a ground, the set bulk nMOS field effect transistors having: a first transistor including: a source coupled to a DC voltage source; and a gate coupled to a digitally controlled oscillator; a second transistor including: a source coupled to the DC voltage source; and a gate coupled to the digitally controlled oscillator; and a third transistor including: a source coupled to a drain of the first transistor; and a drain coupled to a drain of the second transistor. The transistors in the digitally controlled varactor may be FDSOI nMOS devices with backgate coupled to a DC voltage source.
1. A digitally controlled varactor device comprising:
a set of bulk nMOS field effect transistors bulk tied to a ground, the set bulk nMOS field effect transistors having:
a first transistor including:
a source coupled to a DC voltage source; and
a gate coupled to a digitally controlled oscillator;
a second transistor including:
a source coupled to the DC voltage source; and
a gate coupled to the digitally controlled oscillator; and
a third transistor including:
a source coupled to a drain of the first transistor; and
a drain coupled to a drain of the second transistor,
wherein a gate of the first transistor and a gate of the second transistor are coupled to the positive and negative nodes of a digitally controlled oscillator's LC tank.
2. The device of claim 1 , wherein the digitally controlled oscillator's LC tank is biased at approximately 0.5 volts.
3. The device of claim 1 , wherein the DC voltage source provides 0.5 volts to set the first transistor and the second transistor in an off state.
4. The device of claim 1 , wherein a gate of the third transistor receives a control signal.
5. The device of claim 4 , wherein the control signal is in a voltage range of approximately 0 to 1.2 volts.
6. The device of claim 5 , wherein:
in response to the control signal being set to approximately 0 volts, the third transistor is set to an off state; and
in response to the control signal being set to approximately 1.2 volts, the third transistor is set to an on state.
7. The device of claim 1 , wherein the gate of the first transistor and the gate of the second transistor receives a configurable range of voltages through adjustment of a backgate voltage thereof.
8. A digitally controlled varactor device comprising:
a set of FDSOI nMOS field effect transistors gate coupled to a backgate voltage connected to a Vbb potential voltage, the FDSOI nMOS field effect transistors having:
a first transistor including:
a source coupled to a DC voltage source; and
a gate coupled to a digitally controlled oscillator;
a second transistor including:
a source coupled to the DC voltage source; and
a gate coupled to the digitally controlled oscillator; and
a third transistor including:
a source coupled to a drain of the first transistor; and
a drain coupled to a drain of the second transistor,
wherein a gate of the first transistor and a gate of the second transistor are coupled to the positive and negative nodes of a digitally controlled oscillator's LC tank.
9. The device of claim 8 , wherein the digitally controlled oscillator's LC tank is biased at approximately 0.5 volts.
10. The device of claim 8 , wherein the DC voltage source is receiving 0.5 volts to set the first transistor and the second transistor in an off state.
11. The device of claim 8 , wherein a gate of the third transistor receives a control signal.
12. The device of claim 11 , wherein the control signal is in a voltage range of approximately 0 to 1.2 volts.
13. The device of claim 8 , wherein:
in response to the control signal being set to approximately 0 volts, the third transistor is set to an off state; and
in response to the control signal being set to approximately 1.2 volts, the third transistor is set to an on state.
14. The device of claim 8 , wherein the varactor device possesses a range of voltages for a gate of the first transistor and a gate of the second transistor through adjustment of the Vbb potential voltage.
15. A method of achieving very fine frequency tuning resolution, comprising:
applying a bias voltage to a digitally controlled oscillator inductor capacitor (DCO LC) tank that is gate connected to a first NMOS transistor device, and a second NMOS transistor device;
applying a DC biased voltage to a node that is connected to a source of the first NMOS transistor device, and a source of the second NMOS transistor device;
generating a control signal received by a gate of a third NMOS transistor device;
setting a backgate voltage of the first NMOS transistor device, and the second NMOS transistor device, and the third NMOS transistor device to ground; and
adjusting the backgate voltage to reconfigure a tuning range of the DC biased voltage and the control signal.
16. The method of claim 15 , wherein applying the bias voltage to the DCO LC tank includes:
applying a voltage of approximately 0.5 volts to the DCO LC tank.
17. The method of claim 15 , wherein the method includes an array of transistor devices in the DCO LC tank.
18. The method of claim 15 , wherein generating the control signal includes:
generating a range of control signals between approximately 0 to 1.2 volts:
wherein keeping the first NMOS transistor device, and the second NMOS transistor device in the off state through the range;
wherein in response to applying between approximately 0.0 to 0.6 volts to the control signal, the third transistor is set to an off state; and
wherein in response to applying the between approximately 0.9 to 1.2 volts to the control signal, the transistor is set to an on state.