METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE
A method for manufacturing a semiconductor package includes: forming an insulating layer on a support plate; forming a via in the insulating layer; locating a semiconductor device on the insulating layer such that an electrode of the semiconductor device is on the via; removing the support plate; forming a seed layer on a surface of the insulating layer opposite to the semiconductor device, in the via, and on a surface of the electrode of the semiconductor device; and forming a metal layer in the via.
1 . A method for manufacturing a semiconductor package, comprising:
forming an insulating layer on a support plate;
forming a via in the insulating layer;
locating a semiconductor device on the insulating layer such that an electrode of the semiconductor device is on the via;
removing the support plate;
forming a seed layer on a surface of the insulating layer opposite to the semiconductor device, in the via, and on a surface of the electrode of the semiconductor device; and
forming a metal layer in the via.
2 . The method for manufacturing a semiconductor package according to claim 1 , wherein the support plate and the insulating layer are bonded to each other by a first adhesive layer peelable by heat or UV light.
3 . The method for manufacturing a semiconductor package according to claim 1 , wherein the insulating layer and the semiconductor device are bonded to each other by a second adhesive layer adhesive to the semiconductor device in a B stage before being heated and cured and capable of retaining a shape of the via in a heating and curing step.
4 . The method for manufacturing a semiconductor package according to claim 2 , wherein the insulating layer and the semiconductor device are bonded to each other by a second adhesive layer adhesive to the semiconductor device in a B stage before being heated and cured and capable of retaining a shape of the via in a heating and curing step.
5 . The method for manufacturing a semiconductor package according to claim 1 , wherein the via is formed at least by any of laser processing, drill bit processing, and press punching.
6 . The method for manufacturing a semiconductor package according to claim 2 , wherein the via is formed at least by any of laser processing, drill bit processing, and press punching.
7 . The method for manufacturing a semiconductor package according to claim 3 , wherein the via is formed at least by any of laser processing, drill bit processing, and press punching.
8 . The method for manufacturing a semiconductor package according to claim 4 , wherein the via is formed at least by any of laser processing, drill bit processing, and press punching.
9 . The method for manufacturing a semiconductor package according to claim 1 , wherein the insulating layer is formed of a photosensitive resin, and the via is formed by exposure and development.
10 . The method for manufacturing a semiconductor package according to claim 2 , wherein the insulating layer is formed of a photosensitive resin, and the via is formed by exposure and development.
11 . The method for manufacturing a semiconductor package according to claim 3 , wherein the insulating layer is formed of a photosensitive resin, and the via is formed by exposure and development.
12 . The method for manufacturing a semiconductor package according to claim 4 , wherein the insulating layer is formed of a photosensitive resin, and the via is formed by exposure and development.
13 . The method for manufacturing a semiconductor package according to claim 1 , wherein the seed layer is formed by sputtering, and the metal layer is formed by electrolytic plating.
14 . The method for manufacturing a semiconductor package according to claim 1 , wherein the electrode of the semiconductor device is zincate-treated, the seed layer is formed by electroless plating, and the metal layer is formed by electrolytic plating.
15 . A semiconductor package, comprising:
a semiconductor device having an electrode exposed on a surface thereof;
an adhesive layer located on a surface of the semiconductor device;
an insulating layer located on the adhesive layer;
a via running through the adhesive layer and the insulating layer to expose the electrode;
a seed layer provided on a surface of the insulating layer and on an inner wall of the via to be in contact with the electrode;
a metal layer in contact with the seed layer to bury the via; and
a solder ball in contact with the metal layer.
16 . The semiconductor package according to claim 15 , wherein the via is tapered to have a planar size decreasing from the side of the semiconductor device toward the side of the insulating layer.