Fan-out semiconductor package

1. A fan-out semiconductor package comprising:

a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;

a second interconnection member disposed on the active surface of the semiconductor chip; and

a first passivation layer disposed on the second interconnection member,

wherein the second interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip,

the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and

the first passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.

2. The fan-out semiconductor package of claim 1 , wherein a thickness of the first passivation layer is thicker than that of the insulating layer of the second interconnection member.

3. The fan-out semiconductor package of claim 1 , wherein a thickness of the first passivation layer is 10 μm or more.

4. The fan-out semiconductor package of claim 1 , wherein a surface roughness (Ra) of the first passivation layer is 1 nm or more.

5. The fan-out semiconductor package of claim 1 , wherein water absorption of the first passivation layer is 1.5% or less.

6. The fan-out semiconductor package of claim 1 , wherein the insulating layer of the second interconnection member is a photosensitive insulating layer, and

the first passivation layer is a non-photosensitive insulating layer including an inorganic filler.

7. The fan-out semiconductor package of claim 1 , further comprising a first interconnection member having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the first interconnection member,

the first interconnection member includes a first insulating layer, a first redistribution layer in contact with the second interconnection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and

the first and second redistribution layers are electrically connected to the connection pads.

8. The fan-out semiconductor package of claim 7 , wherein the first interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and

the third redistribution layer is electrically connected to the connection pads.

9. The fan-out semiconductor package of claim 8 , further comprising:

a backside redistribution layer disposed on the encapsulant and electrically connected to the third redistribution layer; and

a second passivation layer disposed on the encapsulant and having openings exposing at least portions of the backside redistribution layer.

10. The fan-out semiconductor package of claim 8 , wherein a thickness of the first passivation layer is thicker than that of the insulating layer of the second interconnection member.

11. The fan-out semiconductor package of claim 9 , wherein the second passivation layer is a non-photosensitive insulating layer including an inorganic filler.

12. The fan-out semiconductor package of claim 9 , wherein the second passivation layer comprises a same material as the first passivation layer.

13. The fan-out semiconductor package of claim 9 , further comprising:

a reinforcing layer disposed on the encapsulant; and

a resin layer disposed on the reinforcing layer,

wherein the backside redistribution layer and the second passivation layer are disposed on the resin layer.

14. The fan-out semiconductor package of claim 13 , wherein the reinforcing layer comprises a core material, an inorganic filler, and an insulating resin.

15. The fan-out semiconductor package of claim 8 , wherein a distance between the redistribution layer of the second interconnection member and the first redistribution layer is greater than that between the redistribution layer of the second interconnection member and the connection pads.

16. The fan-out semiconductor package of claim 8 , wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member.

17. The fan-out semiconductor package of claim 8 , wherein a lower surface of the first redistribution layer is disposed on a level above a lower surface of the connection pads.

18. The fan-out semiconductor package of claim 8 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

19. The fan-out semiconductor package of claim 1 , further comprising a first interconnection member having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the first interconnection member,

the first interconnection member includes a first insulating layer, and a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, and

the first and second redistribution layers are electrically connected to the connection pads.

20. The fan-out semiconductor package of claim 19 , wherein the first interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and

the third redistribution layer is electrically connected to the connection pads.

21. The fan-out semiconductor package of claim 20 , wherein the first interconnection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and

the fourth redistribution layer is electrically connected to the connection pads.

22. The fan-out semiconductor package of claim 20 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

23. The fan-out semiconductor package of claim 20 , wherein a thickness of the first passivation layer is thicker than that of the insulating layer of the second interconnection member.

24. The fan-out semiconductor package of claim 20 , wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member.

25. The fan-out semiconductor package of claim 20 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

26. The fan-out semiconductor package of claim 20 , wherein a lower surface of the third redistribution layer is disposed on a level below a lower surface of the connection pads.

27. The fan-out semiconductor package of claim 1 , further comprising an insulating member having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the insulating member.

28. The fan-out semiconductor package of claim 1 , wherein the encapsulant includes an inorganic filler and an insulating resin.

29. The fan-out semiconductor package of claim 1 , further comprising a reinforcing layer disposed on the encapsulant,

wherein the reinforcing layer has a modulus of elasticity greater than that of the encapsulant.

30. The fan-out semiconductor package of claim 1 , further comprising:

openings penetrating through the passivation layer and exposing at least portions of the redistribution layer of the second interconnection member;

an under-bump metal layer formed on the openings and connected to the exposed redistribution layer of the second interconnection member; and

connection terminals formed on the under-bump metal layer, at least one of the connection terminals being disposed in a fan-out region.

31. The fan-out semiconductor package of claim 30 , wherein the under-bump metal layer includes an external connection pad formed on the passivation layer and a plurality of vias formed in the openings and connecting the external connection pad and the redistribution layer of the second interconnection member to each other.

32. The fan-out semiconductor package of claim 31 , wherein a plurality of dimples corresponding to the plurality of vias, respectively, are formed on a surface of the external connection pad.

33. A fan-out semiconductor package comprising:

a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;

a second interconnection member disposed on the active surface of the semiconductor chip; and

a passivation layer disposed on the second interconnection member,

wherein the second interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip,

the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed,

each of the passivation layer and the insulating layer of the second interconnection member includes an inorganic filler and an insulating resin, and

a weight percentage of the inorganic filler included in the passivation layer is greater than that of the inorganic filler included in the insulating layer of the second interconnection member.