Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region
A semiconductor device includes a plurality of gate trenches formed in a semiconductor layer; a gate electrode filled via a gate insulating film in the plurality of gate trenches; an n + -type emitter region, a p-type base region, and an n − -type drift region disposed laterally to each gate trench; a p + -type collector region on a back surface side of the semiconductor layer; a plurality of emitter trenches formed between the gate trenches adjacent to each other; a buried electrode filled via an insulating film in the plurality of emitter trenches; and a p-type floating region formed between the plurality of emitter trenches. The p-type floating region is formed deeper than the p-type base region, and includes an overlap portion. The n + -type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench.
1. A semiconductor device, comprising:
a semiconductor layer;
a plurality of gate trenches formed in the semiconductor layer;
a gate electrode filled via a gate insulating film in the plurality of gate trenches;
an n + -type emitter region, a p-type base region, and an n − -type drift region disposed laterally to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer;
a p + -type collector region disposed on a back surface side of the semiconductor layer with respect to the n − -type drift region;
a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, an emitter trench, which is closest to one gate trench of the plurality of gate trenches, facing the one gate trench across the n − -type drift region throughout from the front surface side of the semiconductor layer to a deepest portion of the emitter trench;
a buried electrode filled via an insulating film in the plurality of emitter trenches, electrically connected with the n + -type emitter region; and
a p-type floating region formed between the plurality of emitter trenches,
wherein the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of an emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench, and
wherein the n + -type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench.
2. The semiconductor device according to claim 1 , wherein the p-type floating region has a bottom portion that bulges to a back surface side of the semiconductor layer with respect to a bottom portion of the emitter trench.
3. The semiconductor device according to claim 1 , wherein the emitter trench is formed at the same depth as that of the gate trench.
4. The semiconductor device according to claim 1 , wherein the gate trenches are disposed one pair each in a transverse direction along the front surface of the semiconductor layer, and the pair of gate trenches are opposed in the transverse direction via the p-type base region that is common thereto.
5. The semiconductor device according to claim 4 , wherein one of the pair of gate trenches is disposed at an interval of 2 μm to 7 μm with respect to the other.
6. The semiconductor device according to claim 1 , wherein the n + -type emitter region has an n-type dopant concentration of 1×10 19 cm −3 to 5×10 20 cm −3 .
7. The semiconductor device according to claim 1 , wherein the p-type base region has a p-type dopant concentration of 1×10 16 cm −3 to 1×10 18 cm −3 .
8. The semiconductor device according to claim 1 , wherein the n − -type drift region has an n-type dopant concentration of 1×10 13 cm −3 to 5×10 14 cm −3 .
9. The semiconductor device according to claim 1 , wherein the p + -type collector region has a p-type dopant concentration of 1×10 15 cm −3 to 2×10 19 cm −3 .
10. The semiconductor device according to claim 1 , wherein
each gate trench is sandwiched between the plurality of emitter trenches, and the p-type base region is formed between the gate trench and the emitter trench.
11. The semiconductor device according to claim 10 , wherein the n + -type emitter regions are formed one each along both side surfaces of the gate trench.
12. The semiconductor device according to claim 10 , wherein the pullout portion is disposed spaced at fixed intervals along a longitudinal direction of the gate trench.
13. The semiconductor device according to claim 12 , wherein the pullout portions of the respective n + -type emitter regions are disposed so that one and the other end portions are opposed to each other across the gate trench.
14. The semiconductor device according to claim 1 , wherein a part of the n − -type drift region is disposed below the p-type floating region, and the semiconductor device further comprising an n-type buffer region disposed between the part of the n − -type drift region and the p + -type collector region.
15. The semiconductor device according to claim 1 , wherein the overlap portion of the p-type floating region has a parabola shape projecting in a direction along the front surface side of the semiconductor layer.