Vertical bit line non-volatile memory systems and methods of fabrication
Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.
1. An apparatus, comprising:
a plurality of global bit lines elongated in a first direction and separated in a second direction substantially orthogonal to the first direction;
a plurality of layer stacks lines elongated in the second direction over the plurality of global bit lines, each layer stack line of the plurality having two vertical sidewalls and including a plurality of silicon layers for a plurality of vertical thin film transistor (TFT) select devices;
a gate dielectric layer extending vertically along the two vertical sidewalls of each layer stack line and over the plurality of global bit lines continuously in the first direction from one vertical sidewall of each layer stack line to an adjacent vertical sidewall of an adjacent layer stack line, wherein the gate dielectric layer includes horizontal portions extending in the first direction over the plurality of global bit lines between adjacent layer stack lines in the first direction and vertical portions extending along the vertical sidewalls of each layer stack line;
a first gate and a second gate elongated in the second direction between adjacent layer stack lines of the plurality, the first gate and the second gate are separated from corresponding layer stack lines by the gate dielectric layer; and
a plurality of dielectric bases elongated in the second direction, wherein each dielectric base extends vertically between a lower surface of the first and second gates and an upper surface of the horizontal portions of the gate dielectric layer.
2. The apparatus of claim 1 , further comprising:
a dielectric fill material extending horizontally between the first gate adjacent to a first layer stack line and the second gate adjacent to a second layer stack line.
3. The apparatus of claim 2 , wherein:
the plurality of dielectric bases extend between adjacent layer stack lines in the first direction.
4. The apparatus of claim 3 , wherein:
the gate dielectric layer extends over the plurality of dielectric bases.
5. The apparatus of claim 3 , wherein:
each dielectric base extends over the gate dielectric layer between adjacent layer stack lines in the first direction.
6. The apparatus of claim 5 , wherein:
the dielectric bases extend over the horizontal portions of the gate dielectric layer and between the vertical portions of the gate dielectric layer.
7. The apparatus of claim 6 , further comprising:
a plurality of word line layers overlying the dielectric fill material;
a plurality of insulating layers overlying the dielectric fill material, each word line layer is separated from an adjacent word line layer by one of the insulating layers;
at least one rewritable memory layer formed along a first and second vertical sidewall of the plurality of word line layers and the plurality of insulating layers; and
a vertical bit line adjacent to the at least one rewritable memory layer; and
wherein the at least one rewritable memory layer forms a plurality of non-volatile storage elements at an intersection of the vertical bit line and one of the word line layers.
8. The apparatus of claim 7 , wherein:
the plurality of non-volatile storage elements is a monolithic three-dimensional array of memory cells positioned above a substrate; and
the plurality of vertical TFT select devices are coupled between a plurality of vertical bit lines and the plurality of global bit lines.
9. An apparatus, comprising:
a first global bit line and a second global bit line elongated in a first direction and separated in a second direction substantially orthogonal to the first direction;
a first vertical thin film transistor (TFT) select device and a second vertical thin film transistor (TFT) select device overlying the first global bit line;
a gate dielectric layer extending vertically along two vertical sidewalls of each layer stack line and horizontally over the first global bit line, wherein the gate dielectric layer includes horizontal portions extending in the first direction over the global bit lines between adjacent layer stack lines in the first direction and vertical portions extending along the vertical sidewalls of each layer stack line;
a dielectric base elongated in the second direction over the first global bit line and the second global bit line and extending in the first direction between the first TFT select device and the second TFT select device; and
a first gate separated from the first TFT select device by the gate dielectric layer; and
a second gate separate from the second TFT select device by the gate dielectric layer, wherein the dielectric base extends vertically between a lower surface of the first and second gates and an upper surface of the horizontal portions of the gate dielectric layer.
10. The apparatus of claim 9 , wherein:
the gate dielectric layer extends over the dielectric base.
11. The apparatus of claim 9 , wherein:
the dielectric base extends over the gate dielectric layer.
12. The apparatus of claim 11 , wherein:
the gate dielectric layer includes a horizontal portion extending in the first direction over the first global bit line between the first TFT select device and the second TFT select device;
the gate dielectric layer includes vertical portions extending along the vertical sidewalls of the first TFT select device and the second TFT select device; and
the dielectric base extends over the horizontal portion of the gate dielectric layer and between the vertical portions of the gate dielectric layer.
13. The apparatus of claim 12 , wherein:
the horizontal portion of the gate dielectric layer extends continuously in the first direction from one vertical sidewall of the first TFT select device to one vertical sidewall of the second TFT select device.
14. An apparatus, comprising:
a first vertical thin film transistor (TFT) select device and a second vertical thin film transistor (TFT) select device overlying a global bit line, the global bit line extending in a first horizontal direction and separated from a second global bit line in a second direction substantially orthogonal to the first horizontal direction;
a gate dielectric layer extending vertically along two vertical sidewalls of the first TFT select device and two vertical sidewalls of the second TFT select device, the gate dielectric layer extending continuously in the first direction from a first vertical sidewall of the first TFT select device to a second vertical sidewall of the second TFT select device;
a first gate separated from the first TFT select device by the gate dielectric layer;
a second gate separated from the second TFT select device by the gate dielectric layer;
a dielectric fill material insulating the first gate from the second gate in the first directions; and
a dielectric base elongated in the second direction over the first global bit line and the second global bit line and extending in the first direction between the first TFT select device and the second TFT select device, wherein the dielectric base extends vertically between the first gate and the gate dielectric layer and vertically between the second gate and the gate dielectric layer.
15. The apparatus of claim 14 , wherein:
the gate dielectric layer extends over the dielectric base.
16. The apparatus of claim 14 , wherein:
the dielectric base extends over the gate dielectric layer.
17. The apparatus of claim 16 , wherein:
the gate dielectric layer includes a horizontal portion extending in the first direction over the first global bit line between the first TFT select device and the second TFT select device;
the gate dielectric layer includes vertical portions extending along the vertical sidewalls of the first TFT select device and the second TFT select device; and
the dielectric base extends over the horizontal portion of the gate dielectric layer and between the vertical portions of the gate dielectric layer.