Methods of forming metal pad structures over TSVS to reduce shorting of upper metal layers
Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.
1. A semiconductor device including a semiconductor die for bonding with another die, the semiconductor die comprising:
a through substrate via (TSV) formed in a substrate of the semiconductor die; and
a pad formed directly over the TSV, wherein the pad comprises a plurality of metal bars extending in a first direction, the plurality of metal bars being separated by a plurality of dielectric bars extending in the first direction, the plurality of metal bars and the plurality of dielectric bars having an alternating pattern in a region directly over the TSV.
2. The semiconductor device of claim 1 , further comprising an interconnect structure electrically connected to the pad.
3. The semiconductor device of claim 2 , further comprising a second die bonded to the interconnect structure.
4. The semiconductor device of claim 1 , wherein the TSV has a first width measured in a second direction orthogonal to the first direction, and the pad has a second width measured in the second direction, the second width being greater than the first width.
5. The semiconductor device of claim 1 , wherein each metal bar of the plurality of metal bars has a same width.
6. The semiconductor device of claim 1 , wherein at least one metal bar of the plurality of metal bars has a first width at a first end of the metal bar and a second width at a middle of the metal bar, the second width being smaller than the first width.
7. The semiconductor device of claim 1 , wherein at least two metal bars of the plurality of metal bars extending are connected by a metal strip, the metal strip extending in a second direction orthogonal to the first direction.
8. The semiconductor device of claim 1 , wherein the plurality of dielectric bars respectively include an etch stop layer surrounding the dielectric bars.
9. The semiconductor device of claim 1 , wherein the plurality of metal bars respectively include a barrier layer on sidewalls of the metal bars.
10. A semiconductor die for bonding with another die, comprising:
a through substrate via (TSV) extending through a substrate; and
a metal pad formed directly over the TSV, the metal pad comprising a plurality of apertures formed therein, the plurality of apertures being completely filled by a dielectric material.
11. The semiconductor die of claim 10 , wherein each of the plurality of apertures is substantially rectangular.
12. The semiconductor die of claim 10 , wherein each of the plurality of apertures has a first width at an end region and a second width at a middle region, and wherein the first width is smaller than the second width.
13. The semiconductor die of claim 10 , wherein in a top down view, the plurality of apertures comprises a first plurality of apertures positioned in a central region of the metal pad, a second plurality of apertures vertically spaced from ends of the first plurality of apertures, and a third plurality of apertures horizontally spaced from edges of the first plurality and the second plurality of apertures.
14. The semiconductor die for bonding with another die of claim 10 , wherein the metal pad includes a barrier layer.
15. The semiconductor die for bonding with another die of claim 10 , wherein the dielectric material comprises an etch stop layer and a dielectric layer different from the etch stop layer disposed over the etch stop layer.
16. A semiconductor device including a semiconductor die, the semiconductor device comprising:
a through substrate via (TSV) formed in a substrate of the semiconductor die; and
a metal pad formed directly over the TSV, wherein the metal pad comprises a first plurality of metal bars extending in a first direction and a second plurality of metal bars extending in a second direction perpendicular to the first direction; and
dielectric bars between each of the first plurality of metal bars, wherein an upper surface of each of the first plurality of metal bars, an upper surface of each of the second plurality of metal bars, and an upper surface of the dielectric bars are substantially coplanar.
17. The semiconductor device of claim 16 , further comprising a third plurality of metal bars extending in the first direction, each of the third plurality of metal bars having a first width and each of the first plurality of metal bars having a second width, the first width being greater than the second width.
18. The semiconductor device of claim 16 , further comprising an interconnect structure electrically connected to the metal pad.
19. The semiconductor device of claim 18 , further comprising a second die bonded to the interconnect structure.
20. The semiconductor device of claim 18 , wherein at least one metal bar of the first plurality of metal bars has a first width at a first end of the metal bar and a second width at a middle of the metal bar, the second width being narrower than the first width.