Semiconductor die contact structure and method
A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.
1. A semiconductor device comprising:
a metal contact over a substrate, the metal contact having a thickness of at least 15,000 Å, wherein a first material is located throughout the metal contact;
a contact pad in electrical connection with the metal contact, wherein an external sidewall of the contact pad is located directly over the metal contact, wherein the contact pad has a U-shape and has a width that is less than the metal contact;
a first passivation layer located at least partially between the metal contact and the contact pad in a direction perpendicular to a major surface of the substrate;
a plurality of dielectric layers located between the metal contact and the substrate, the plurality of dielectric layers comprising an extra low-k dielectric material;
an underbump metallization in physical contact with the contact pad;
a second passivation layer located at least partially between the underbump metallization and the contact pad; and
an external contact in physical contact with the underbump metallization.
2. The semiconductor device of claim 1 , wherein the metal contact has a thickness of about 20,000 Å.
3. The semiconductor device of claim 1 , wherein the contact pad has a thickness between about 10,000 Å and about 50,000 Å.
4. The semiconductor device of claim 1 , wherein the first passivation layer comprises a first material and the second passivation layer comprises the first material.
5. The semiconductor device of claim 4 , further comprising a third passivation layer adjacent to the metal contact, wherein the third passivation layer comprises the first material.
6. The semiconductor device of claim 1 , further comprising a polyimide coating located on the second passivation layer.
7. The semiconductor device of claim 1 , wherein the underbump metallization is a copper titanium alloy.
8. A semiconductor device comprising:
a plurality of extra low-k dielectric layers over a semiconductor substrate;
a buffer contact located over the plurality of extra low-k dielectric layers, the buffer contact being at least 15,000 Å in thickness;
a U-shaped contact in physical connection with the buffer contact, the U-shaped contact having a smaller width than the buffer contact, the U-shaped contact comprising a recess;
an underbump metallization extending into the recess; and
a conductive pillar adjacent to the underbump metallization and also extending into the recess.
9. The semiconductor device of claim 8 , wherein the underbump metallization has a thickness of between about 0.1 μm and about 2 μm.
10. The semiconductor device of claim 8 , wherein the conductive pillar has a width of between about 10 μm and about 200 μm.
11. The semiconductor device of claim 8 , further comprising a conductive barrier layer over the conductive pillar.
12. The semiconductor device of claim 11 , wherein the conductive barrier layer comprises nickel.
13. The semiconductor device of claim 8 , wherein the conductive pillar has a first sidewall and the underbump metallization has a second sidewall aligned with the first sidewall.
14. A semiconductor device comprising:
a single metal material over an extra low-k dielectric layer, the single metal material having a first width and a first thickness, the first thickness being greater than 15,000 Å;
a contact pad in electrical connection with the single metal material, the contact pad having a U shape and a second width less than the first width;
a first passivation layer located over the contact pad;
a first opening through the first passivation layer and exposing the contact pad, the first opening having a first width;
a second passivation layer located over the contact pad; and
a second opening through the second passivation layer and exposing the contact pad, the second opening having a second width less than the first width.
15. The semiconductor device of claim 14 , further comprising an underbump metallization extending at least partially into the second opening.
16. The semiconductor device of claim 15 , an external contact in electrical connection with and physically aligned with the underbump metallization.
17. The semiconductor device of claim 16 , further comprising a protective layer over the external contact.
18. The semiconductor device of claim 17 , wherein the protective layer has a thickness between 500 Å and 5000 Å.
19. The semiconductor device of claim 18 , wherein the protective layer has a thickness between 500 Å and 2000 Å.
20. The semiconductor device of claim 16 , wherein the external contact is a copper pillar.