Semiconductor structure and method for reviewing defects
View Patent ↗A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
1. A semiconductor structure comprising:
a wafer comprising a plurality of viewing fields defined thereon;
a plurality of dies defined by a scribe line formed in each viewing field;
a plurality of mark patterns formed in the scribe line; and
a plurality of anchor patterns respectively formed in the review fields, the anchor patterns being different from the mark patterns.
2. The semiconductor structure according to claim 1 , wherein the viewing fields are defined in a photolithography process and identified by a defect review apparatus.
3. The semiconductor structure according to claim 1 , wherein the mark patterns comprise alignment mark patterns.
4. The semiconductor structure according to claim 1 , wherein the anchor patterns are formed in the scribe line at a corner of the dies, respectively.
5. The semiconductor structure according to claim 4 , wherein the anchor patterns are formed at the corner of the dies located at a corner of the viewing fields.
6. The semiconductor structure according to claim 4 , wherein the anchor patterns are formed at the corner of the dies not located at a corner of the viewing fields.
7. The semiconductor structure according to claim 1 , wherein the anchor patterns and mark patterns comprise different shapes.
8. The semiconductor structure according to claim 1 , wherein the anchor patterns respectively comprise a plurality of sub-patterns arranged therein, and at least a programmed defect is formed in one of the sub-patterns.
9. The semiconductor structure according to claim 8 , wherein the sub-patterns comprise semiconductor patterns, metal patterns, or insulating patterns.
10. The semiconductor structure according to claim 8 , wherein the programmed defect comprises a gap defect, a short-end defect, or a bridge defect.