IP Library Granted Patent US 10,586,748
Granted Patent B2
US 10,586,748 · App. 15/402,876 · Granted Mar 10, 2020

Printed circuit board and semiconductor package

Inventor: Soo-Jae Park (Asan-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L23/3121H01L21/4857H01L21/6835H01L23/49822H01L23/49827H01L24/48H01L24/45H01L2221/68345H01L2221/68359H01L2221/68381H01L2224/32225H01L2224/45144H01L2224/45147H01L2224/48091H01L2224/48106H01L2224/48227H01L2224/48228H01L2224/48229H01L2224/48235H01L2224/73265H01L2224/85395H01L2224/85424H01L2924/01013H01L2924/01022H01L2924/01028H01L2924/01029H01L2924/01047H01L2924/01073H01L2924/01074H01L2924/01078H01L2924/01079H01L2924/04941H01L2924/04953H01L2924/05432H01L2924/1443H01L2924/1579H01L2924/15724H01L2924/181H01L2924/403H01L2924/40252H01L2924/40404
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,586,748
App. No.
15/402,876
Granted
Mar 10, 2020
Kind
B2
Abstract

A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.

Claims (15)

1. A printed circuit board (PCB), comprising:

an insulating layer that includes an upper surface and a lower surface opposite to the upper surface;

a first conductive pattern on the upper surface of the insulating layer;

a second conductive pattern on the lower surface of the insulating layer;

a first solder resist layer with an opening on the insulating layer;

an aluminum pattern that covers an upper surface of the first conductive pattern;

a second passivation layer is disposed on and directly contacts a portion of a first surface of the second conductive pattern opposite at second surface of the second conductive pattern, wherein the second surface of the second conductive pattern directly contacts the lower surface of the insulating layer; and

first passivation layers that cover a side surface of part of the first conductive pattern exposed by the opening of the first solder resist layer,

wherein spaces are formed between each of the first passivation layers.

2. The PCB of claim 1 , wherein the upper surface of the first conductive pattern is higher than the upper surface of the insulating layer.

3. The PCB of claim 1 , wherein the first passivation layers comprises a material formed through an organic solderability preservative (OSP) surface treatment.

4. The PCB of claim 1 , further comprising a second solder resist layer on the lower surface of the insulating layer,

wherein the second solder resist layer covers sides of the second conductive pattern.

5. The PCB of claim 1 , further comprising:

a barrier pattern between the first conductive pattern and the aluminum pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2017
From: PARK, SOO-JAE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 040937/0553 →
Priority Claims (1)
KR 10-2016-0049384 · Apr 22, 2016 · national
Continuity (1)
Related Publication 20170309559A1 · Oct 26, 2017
Cited By (1)
US 12,243,813