IP Library Granted Patent US 12,243,813
Granted Patent B2
US 12,243,813 · App. 18/483,884 · Granted Mar 4, 2025

Connection structure and method of forming the same

Inventor: Jongyoun Kim (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L23/49838H01L21/4857H01L23/49816H01L23/49822H01L23/49827H05K1/11H05K1/111H05K1/182H01L23/3128H01L23/3135H01L23/5383H01L24/16H01L24/48H01L25/0657H01L2224/16227H01L2224/48229H05K1/0284H05K1/0298H05K1/0306H05K1/0313H05K1/115H05K1/18H05K1/181H05K2201/10378
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,243,813
App. No.
18/483,884
Granted
Mar 4, 2025
Kind
B2
Abstract

Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

Claims (65)

1. A connection structure comprising:

a first passivation layer;

a first conductive pattern that penetrates the first passivation layer and partially protrudes upwardly from the first passivation layer;

a second passivation layer on the first passivation layer and covering the first conductive pattern;

a second conductive pattern on the second passivation layer, the second conductive pattern comprises a second head segment that horizontally extends on an uppermost surface of the second passivation layer and a second tail segment that vertically penetrates the second passivation layer and connected to the first conductive pattern;

a third passivation layer on the second passivation layer and covering the second conductive pattern; and

a third conductive pattern on the third passivation layer, the third conductive pattern comprises a third head segment that horizontally extends on an uppermost surface of the third passivation layer and a third tail segment that vertically penetrates the third passivation layer;

wherein a thickness of the third head segment is greater than a thickness of the second head segment, and smaller than a thickness of the first conductive pattern, and

wherein the second passivation layer is the thickest among the first passivation layer, the second passivation layer, and the third passivation layer.

2. The connection structure as claimed in claim 1 , wherein a bottom surface of the first conductive pattern is coplanar with an uppermost surface of the first passivation layer,

wherein a bottom surface of the second head segment is coplanar with the uppermost surface of the second passivation layer, and

wherein a bottom surface of the third head segment is coplanar with the uppermost surface of the third passivation layer.

3. The connection structure as claimed in claim 1 , wherein a width of the first conductive pattern is greater than a width of the second head segment, and the width of the second head segment is greater than a width of the third head segment.

4. The connection structure as claimed in claim 1 , wherein a pitch between patterns of the first conductive pattern is equal to or greater than a pitch between patterns of the second conductive pattern, and the pitch between the patterns of the second conductive pattern is equal to or greater than a pitch between patterns of the third conductive pattern.

5. The connection structure as claimed in claim 1 , wherein the first conductive pattern is thicker than the third conductive pattern, and the third conductive pattern is thicker than the second conductive pattern.

6. The connection structure of claim 1 , further comprising an additional pattern on at least one from among the first passivation layer and the second passivation layer.

7. The connection structure of claim 6 , wherein the additional pattern is formed between patterns of the first conductive pattern or between patterns of the second conductive pattern.

8. The connection structure of claim 7 , wherein the additional pattern is one of:

a dummy pattern electrically isolated on the at least one from among the first passivation layer and the second passivation layer; and

a pattern either for electrical power delivery or for electrical ground.

9. The connection structure of claim 1 , further comprising a first seed pattern between the first conductive pattern and the first passivation layer,

the first seed pattern is not provided on a bottom surface of the first conductive pattern.

10. The connection structure of claim 9 , further comprising a second seed pattern on a bottom surface of the second conductive pattern, the bottom surface of the second conductive pattern facing the first conductive pattern.

11. A semiconductor package, comprising:

a connection structure;

a semiconductor chip mounted on the connection structure; and

a molding layer covering the semiconductor chip on the connection structure,

wherein the connection structure comprises:

a first passivation layer;

a first conductive pattern that penetrates the first passivation layer and partially protrudes upwardly from the first passivation layer;

a second passivation layer on the first passivation layer and covering the first conductive pattern;

a second conductive pattern that penetrates the second passivation layer and partially protrudes upwardly from the second passivation layer, the second conductive pattern comprises a second head segment that horizontally extends on an uppermost surface of the second passivation layer;

a third passivation layer on the second passivation layer and covering the second conductive pattern; and

a third conductive pattern that penetrates the third passivation layer and partially protrudes upwardly from the third passivation layer, the third conductive pattern comprises a third head segment that horizontally extends on an uppermost surface of the third passivation layer,

wherein a thickness of the third head segment is greater than a thickness of the second head segment, and smaller than a thickness of the first conductive pattern,

wherein a thickness of second passivation layer is greater than a thickness of the first passivation layer, and

wherein the second passivation layer is the thickest among the first passivation layer, the second passivation layer, and the third passivation layer.

12. The semiconductor package as claimed in claim 11 , wherein a width of the first conductive pattern is greater than a width of the second head segment.

13. The semiconductor package as claimed in claim 11 , wherein a pitch between patterns of the first conductive pattern is equal to or greater than a pitch between patterns of the second conductive pattern, and the pitch between patterns of the second conductive pattern is equal to or greater than a pitch between patterns of the third conductive pattern.

14. The semiconductor package as claimed in claim 11 ,

wherein the first conductive pattern comprises:

a first head segment that horizontally extends on an uppermost surface of the first passivation layer, wherein a bottom surface of the first head segment is coplanar with the uppermost surface of the first passivation layer; and

a first tail segment that vertically penetrates the first passivation layer,

wherein the second conductive pattern further comprises a second tail segment that vertically penetrates the second passivation layer and has connection with the first conductive pattern.

15. The semiconductor package as claimed in claim 11 , wherein the semiconductor chip is mounted on the third conductive pattern through connection terminals,

wherein the connection terminals connect the third conductive pattern and chip pads of the semiconductor chip.

16. A connection structure comprising:

a first passivation layer;

a first conductive pattern disposed on and penetrating the first passivation layer;

a second passivation layer on the first passivation layer and covering the first conductive pattern;

a second conductive pattern disposed on and penetrating the second passivation layer, the second conductive pattern comprises a second head segment that horizontally extends on an uppermost surface of the second passivation layer;

a third passivation layer on the second passivation layer and covering the second conductive pattern; and

a third conductive pattern disposed on and penetrating the third passivation layer, the third conductive pattern comprises a third head segment that horizontally extends on an uppermost surface of the third passivation layer,

wherein a thickness of the third head segment is greater than a thickness of the second head segment, and smaller than a thickness of the first conductive pattern,

wherein a thickness of second passivation layer is greater than a thickness of the first passivation layer,

wherein a width of the first conductive pattern is greater than a width of the second head segment,

wherein a pitch between patterns of the first conductive pattern is greater than a pitch between patterns of the second conductive pattern, and

wherein the second passivation layer is the thickest among the first passivation layer, the second passivation layer, and the third passivation layer.

17. The connection structure of claim 16 , wherein the width of the second head segment is equal to or greater than a width of the third head segment, and

wherein the pitch between the patterns of the second conductive pattern is equal to or greater than a pitch between patterns of the third conductive pattern.

18. The connection structure as claimed in claim 16 ,

wherein the first conductive pattern comprises:

a first head segment that horizontally extends on an uppermost surface of the first passivation layer, wherein a bottom surface of the first head segment is coplanar with the uppermost surface of the first passivation layer; and

a first tail segment that vertically penetrates the first passivation layer,

wherein the second conductive pattern further comprises a second tail segment that vertically penetrates the second passivation layer and has connection with the first conductive pattern.

Priority Claims (1)
KR 10-2018-0155947 · Dec 6, 2018 · national
Continuity (4)
Continuation 17857696 · Jul 5, 2022
Continuation 17085436 · Oct 30, 2020
Continuation 16447441 · Jun 20, 2019
Related Publication 20240055344A1 · Feb 15, 2024
References Cited (30)
US 9425178B2 · Lin et al. · 2016 [cited by applicant]
US 9431367B2 · Lin et al. · 2016 [cited by applicant]
US 9576931B1 · Shih · 2017 [cited by applicant]
US 9620482B1 · Chen et al. · 2017 [cited by applicant]
US 9756738B2 · Hu · 2017 [cited by applicant]
US 9806063B2 · Kim et al. · 2017 [cited by applicant]
US 9820391B2 · Shimizu · 2017 [cited by examiner]
US 9837347B2 · Hu · 2017 [cited by examiner]
US 9887148B1 · Huang et al. · 2018 [cited by applicant]
US 10014260B2 · Tsai et al. · 2018 [cited by applicant]
US 10319650B2 · Kim et al. · 2019 [cited by applicant]
US 10586748B2 · Park et al. · 2020 [cited by applicant]
US 11437310B2 · Kim · 2022 [cited by applicant]
US 20030178229A1 · Toyoda et al. · 2003 [cited by applicant]
US 20120028458A1 · Cabral, Jr. et al. · 2012 [cited by applicant]
US 20150016079A1 · Furutani et al. · 2015 [cited by applicant]
US 20150145628A1 · Kim · 2015 [cited by examiner]
US 20160056100A1 · Yeh · 2016 [cited by applicant]
US 20160064309A1 · Su et al. · 2016 [cited by applicant]
US 20160141255A1 · Lu et al. · 2016 [cited by applicant]
US 20160141262A1 · Hu · 2016 [cited by applicant]
US 20180130749A1 · Tsai et al. · 2018 [cited by applicant]
US 20180308800A1 · Tsai · 2018 [cited by examiner]
US 20200013721A1 · Chiang et al. · 2020 [cited by applicant]
CN 107306477A · 2017 [cited by applicant]
CN 107818965A · 2018 [cited by applicant]
KR 1020090092032A · 2009 [cited by applicant]
KR 101707931B1 · 2017 [cited by applicant]
KR 1020170099513A · 2017 [cited by applicant]
KR 1020170103533A · 2017 [cited by applicant]