IP Library › Granted Patent US 10,103,098
Granted Patent B2
US 10,103,098 · App. 15/403,480 · Granted Oct 16, 2018

Semiconductor devices including a through via structure and methods of forming the same

Inventors: Deokyoung Jung (Seoul, KR); Kwangjin Moon (Hwaseong-si, KR); Byung Lyul Park (Seoul, KR); Jin Ho An (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L23/5226H01L23/481H01L23/53238H01L23/53295H01L23/53266H01L2224/0401H01L2224/05572H01L2224/131H01L2225/06544
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Quick Facts
Patent No.
US 10,103,098
App. No.
15/403,480
Granted
Oct 16, 2018
Kind
B2
Abstract

Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor substrate including a first surface and a second surface opposite the first surface, a front insulating layer on the first surface of the semiconductor substrate, a back insulating layer on the second surface of the semiconductor substrate, a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, a via insulating layer on a side surface of the through via structure, and a contact structure extending through the front insulating layer. The through via structure may include a first region and a second region disposed on the first region. The second region may include a first doping element, and the first region may be substantially free of the first doping element.

Claims (59)

1. A semiconductor device, comprising:

a semiconductor substrate including a first surface and a second surface opposite the first surface;

a front insulating layer on the first surface of the semiconductor substrate;

a back insulating layer on the second surface of the semiconductor substrate;

a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, the through via structure including a first region and a second region disposed on the first region, the second region including a first doping element, the first region being substantially free of the first doping element, the second region being closer to the front insulating layer than the back insulating layer, and the second region being spaced apart from the front insulating layer;

a via insulating layer on a side surface of the through via structure; and

a contact structure extending through the front insulating layer.

2. The device of claim 1 , further comprising:

an inter-metal insulating layer on the front insulating layer;

a via pad extending through the inter-metal insulating layer and being electrically connected to the through via structure; and

a wiring structure extending through the inter-metal insulating layer and being electrically connected to the contact structure.

3. The device of claim 2 , wherein:

the via pad comprises a same material as the wiring structure; and

upper surfaces of the via pad and the wiring structure are coplanar.

4. The device of claim 2 , wherein:

the via pad includes a first portion that overlaps the through via structure in plan view and a second portion that does not overlap the through via structure in plan view; and

a lower surface of the second portion of the via pad is lower than an upper surface of the front insulating layer relative to the first surface of the semiconductor substrate.

5. The device of claim 2 , wherein:

the via pad includes line portions and a connection portion connecting end portions of the line portions;

the line portions of the via pad cross an upper surface of the through via structure and extend onto the front insulating layer; and

the connection portion of the via pad is on the front insulating layer.

6. The device of claim 5 , further comprising a connection wiring on the via pad,

wherein the connection wiring is electrically connected to the connection portion of the via pad.

7. The device of claim 2 , wherein the wiring structure includes a first side surface that overlaps an upper surface of the contact structure in plan view and a second side surface that does not overlap the upper surface of the contact structure in plan view.

8. The device of claim 1 , wherein the second region further includes a second doping element and a third doping element, and

wherein the first doping element is silicon (Si), the second doping element is nitrogen (N), and the third doping element is oxygen (O).

9. The device of claim 1 , wherein an upper surface of the through via structure is at a higher level than a lower surface of the front insulating layer relative to the first surface of the semiconductor substrate.

10. A semiconductor device, comprising:

a semiconductor substrate including a first surface and a second surface opposite the first surface;

a front lower insulating layer on the first surface of the semiconductor substrate;

a back insulating layer on the second surface of the semiconductor substrate;

a through via structure extending through the semiconductor substrate, the front lower insulating layer, and the back insulating layer, wherein the through via structure includes a first region and a second region disposed on the first region, and wherein the second region of the through via structure includes a first doping element, and the first region of the through via structure is substantially free of the first doping element;

a via insulating layer on a side surface of the through via structure;

a contact structure on the first surface of the semiconductor substrate and in the front lower insulating layer;

an inter-metal insulating layer on the front lower insulating layer, the front lower insulating layer being between the semiconductor substrate and the inter-metal insulating layer;

a via pad extending through the inter-metal insulating layer and contacting the second region of the through via structure; and

a wiring structure extending through the inter-metal insulating layer and being electrically connected to the contact structure.

11. The device of claim 10 , wherein the via pad contacts an upper surface of the through via structure and an upper portion of the side surface of the through via structure.

12. The device of claim 10 , wherein the through via structure further includes a third region disposed under the first region, and the first region is between the second region and the third region, and

wherein the third region of the through via structure further includes a second doping element that is substantially absent from the first region.

13. A semiconductor device, comprising:

a substrate;

a through via structure extending through the substrate, the through via structure comprising a metal electrode that extends through the substrate and comprises a first surface and a second surface opposite the first surface, and the metal electrode comprising a first portion that comprises the first surface of the metal electrode and comprises a first chemical element that is silicon, oxygen or nitrogen;

a via pad extending on the first surface of the metal electrode and contacting the first portion of the metal electrode; and

an insulating layer on the substrate, the insulating layer comprising a lower surface facing the substrate and an upper surface opposite the lower surface of the insulating layer,

wherein the via pad extends on a portion of a side surface of the through via structure,

wherein the through via structure and the metal electrode are in the insulating layer,

wherein the insulating layer comprises an upper portion that comprises the upper surface of the insulating layer and comprises the first chemical element, and

wherein a lower portion of the insulating layer is substantially free of the first chemical element.

14. The device of claim 13 , wherein the metal electrode comprises a second portion that is adjacent the first portion, and

wherein the second portion of the metal electrode is substantially free of the first chemical element.

15. The device of claim 13 ,

wherein the through via structure and the metal electrode extend through the insulating layer, and

wherein the first surface of the metal electrode is higher than the upper surface of the insulating layer relative to a surface of the substrate.

16. The device of claim 15 , further comprising a conductive contact extending through the insulating layer,

wherein the upper surface of the insulating layer and an upper surface of the conductive contact are coplanar.

17. The device of claim 16 , wherein the conductive contact comprises an upper portion that comprises the upper surface of the conductive contact and comprises the first chemical element.

18. The device of claim 13 , wherein the via pad contacts the first surface of the metal electrode and the portion of the side surface of the through via structure.

19. The device of claim 10 , wherein the first doping element is silicon, nitrogen or oxygen.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2017
From: JUNG, DEOKYOUNG; MOON, KWANGJIN; PARK, BYUNG LYUL; AN, JIN HO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 040946/0071 →
Priority Claims (1)
KR 10-2016-0003482 · Jan 12, 2016 · national
Continuity (1)
Related Publication 20170200675A1 · Jul 13, 2017
Cited By (1)
US 12,690,446