IP Library Granted Patent US 9,941,375
Granted Patent B2
US 9,941,375 · App. 15/417,436 · Granted Apr 10, 2018

Method for manufacturing a semiconductor device having silicide layers

Inventors: Rolf Weis (Dresden, DE); Martin Bartels (Dresden, DE); Marko Lemke (Dresden, DE); Stefan Tegen (Dresden, DE)
Assignee: Infineon Technologies Dresden GmbH
H01L29/45H01L21/28518H01L29/0696H01L29/1095H01L29/66696H01L29/7825
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Quick Facts
Patent No.
US 9,941,375
App. No.
15/417,436
Granted
Apr 10, 2018
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.

Claims (20)

1. A method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate having a first side;

forming a trench having a bottom, the trench extending from the first side of the semiconductor substrate into the semiconductor substrate and separating a first mesa region formed in the semiconductor substrate from a second mesa region formed in the semiconductor substrate;

filling the trench with an insulating material;

removing the second mesa region relative to the insulating material filled in the trench to form a recess in the semiconductor substrate, the recess having at least one side wall covered with the insulating material and a bottom; and

forming, in a common process, a first silicide layer on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer on and in contact with the bottom of the recess.

2. The method of claim 1 , wherein a distance between the first side of the semiconductor substrate and the bottom of the recess is at least 500 nm.

3. The method of claim 1 , further comprising:

depositing a common metal layer on and in contact with the first silicide layer and on and in contact with the second silicide layer;

forming a mask layer on the metal layer; and

etching the common metal layer using the mask layer as an etching mask to form a first metal layer on and in contact with the first silicide layer and a second metal layer on and in contact with the second silicide layer.

4. The method of claim 1 , further comprising:

forming a first doping region in the first mesa region, wherein the first silicide layer is in ohmic contact with the first doping region; and

forming a second doping region in the semiconductor substrate at the bottom of the recess, wherein the second silicide layer is in ohmic contact with the second doping region.

5. The method of claim 1 , wherein the trench completely laterally surrounds the second mesa region when viewed in plane projection onto the first side of the semiconductor substrate.

6. The method of claim 1 , wherein the second mesa region forms, when viewed in plane projection onto the first side of the semiconductor substrate, a closed ring structure, wherein the second mesa region is laterally bound by an inner trench and an outer trench.

7. The method of claim 1 , further comprising:

depositing a metal liner comprising at least a silicide-forming metal on the first side of the semiconductor substrate and in the recess;

conducting a thermal treatment so that the silicide-forming metal of the metal liner reacts with exposed regions of the semiconductor substrate to form the first and second silicide layers; and

removing unreacted silicide-forming metal from the insulating material.

Assignments (2)
CHANGE OF NAME Recorded Jun 12, 2024
From: INFINEON TECHNOLOGIES DRESDEN GMBH
To: INFINEON TECHNOLOGIES DRESDEN GMBH & CO. KG
Reel/Frame 067699/0648 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2017
From: WEIS, ROLF; BARTELS, MARTIN; LEMKE, MARKO; TEGEN, STEFAN
To: INFINEON TECHNOLOGIES DRESDEN GMBH
Reel/Frame 041821/0009 →
Priority Claims (1)
DE 10 2016 101 545 · Jan 28, 2016 · national
Continuity (1)
Related Publication 20170222010A1 · Aug 3, 2017