Semiconductor device including a clock source for generating a clock signal and a clock control circuit for controlling the clock source in hardware, a semiconductor system including the semiconductor device, and a method of operating the semiconductor device
A semiconductor device includes a first intellectual property block (IP block) which includes a function unit and an interface unit; a first clock control circuit which controls a first clock source; a second clock control circuit which transmits a first clock request to the first clock control circuit, and controls a second clock source which receives a clock signal from the first clock source; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block; wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.
1. A semiconductor device, comprising:
a first intellectual property block (IP block) which comprises a function unit and an interface unit;
a first clock control circuit which controls a first clock source;
a second clock control circuit which transmits a first clock request to the first clock control circuit, controls a second clock source which receives a clock signal from the first clock source, and provides the clock signal directly to the first IP block; and
a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block,
wherein, in response to the clock stop request from the first IP block, the second clock control circuit disables the second clock source and transmits a request for clock provision stop as the first clock source to the first clock control circuit,
wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.
2. The semiconductor device of claim 1 , wherein the interface unit receives information on an operating state of the function unit of the first IP block, and the operating state comprises a sleep state or a running state.
3. The semiconductor device of claim 1 , wherein the interface unit receives the first signal which is provided from the second IP block, while the function unit of the first IP block is in a sleep state.
4. The semiconductor device of claim 3 , wherein the interface unit transmits the clock stop request to the channel management circuit after receiving the first signal.
5. The semiconductor device of claim 3 , wherein the interface unit generates a second signal corresponding to the first signal, after the function unit of the first IP block wakes up.
6. The semiconductor device of claim 5 , wherein the interface unit provides the second signal to the function unit, after the function unit of the first IP block wakes up.
7. The semiconductor device of claim 1 , wherein the first IP block is a slave device, and the second IP block is a master device.
8. The semiconductor device of claim 1 , wherein the first signal comprises a bus operation signal.
9. The semiconductor device of claim 8 , wherein the bus operation signal comprises an address signal, a data signal, or a control signal.
10. The semiconductor device of claim 8 , wherein the function unit of the first IP block performs a bus operation with the second IP block, after receiving the first signal from the interface unit.
11. A semiconductor device, comprising:
a master intellectual property (IP) block which operates in response to a first clock signal provided from a clock management unit (CMU); and
a slave IP block which comprises a function unit which operates in response to a second clock signal provided from the CMU, and an interface unit configured to receive a bus operation signal from the master IP block at a first time point and provide the bus operation signal to the function unit at a second time point different from the first time point,
wherein the CMU includes a first clock source for providing the first clock signal, the first clock source being controlled by a first clock control circuit, a second clock source for providing the second clock signal, and a third clock source for providing a third clock signal to the first and second clock sources, wherein the first and second clock signals are based on the third clock signal, and
wherein, in response to a clock stop request from the slave IP block, a second clock control circuit disables the second clock source and transmits a request for clock provision stop to a third clock control circuit that controls the third clock source.
12. The semiconductor device of claim 11 , wherein the interface unit receives information on an operating state of the function unit, and the operating state comprises a sleep state or a running state.
13. The semiconductor device of claim 11 , wherein the interface unit receives the bus operation signal from the master IP block when the function unit is in the sleep state.
14. The semiconductor device of claim 13 , wherein the interface unit transmits a clock request to the CMU, after receiving the bus operation signal from the master IP block.
15. The semiconductor device of claim 13 , wherein the interface unit provides the bus operation signal to the function unit, at the second time point when the function unit wakes up.
16. The semiconductor device of claim 15 , wherein the function unit performs the bus operation with the master IP block, after receiving the bus operation signal from the interface unit.
17. The semiconductor device of claim 11 , wherein the bus operation signal comprises an address signal, a data signal, or a control signal.
18. The semiconductor device of claim 11 , wherein the master IP block and the slave IP block transmit and receive data, in accordance with an advanced peripheral bus protocol (APB protocol) or an advanced high-performance bus protocol (AHB protocol).
19. The semiconductor device of claim 18 , wherein the master IP block comprises an APB bridge block.
20. A semiconductor system, comprising:
a system-on-chip (SoC) comprising:
a first intellectual property block (IP block) which comprises a function unit and an interface unit;
a second IP block electrically connected to the first IP block;
a first clock control circuit which controls a first clock source;
a second clock control circuit which transmits a first clock request to the first clock control circuit, controls a second clock source which receives a clock signal from the first clock source, and provides the clock signal directly to the first IP block; and
a channel management circuit which transmits a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block, and
one or more external devices electrically connected to the SoC,
wherein, in response to the clock stop request from the first IP block, the second clock control circuit disables the second clock source and transmits a request for clock provision stop as the first clock source to the first clock control circuit,
wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from the second IP block and provides the first signal to the function unit.