IP Library Granted Patent US 10,840,354
Granted Patent B2
US 10,840,354 · App. 15/425,496 · Granted Nov 17, 2020

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

Inventors: Zhenxing Bi (Niskayuna, NY); Thamarai S. Devarajan (Albany, NY); Balasubramanian Pranatharthiharan (Watervliet, NY); Sanjay C. Mehta (Niskayuna, NY); Muthumanickam Sankarapandian (Niskayuna, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/66553H01L29/0649H01L29/4966H01L29/66666H01L29/7827H01L29/78642
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Quick Facts
Patent No.
US 10,840,354
App. No.
15/425,496
Granted
Nov 17, 2020
Kind
B2
Abstract

A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Claims (11)

1. A semiconductor device, comprising:

one or more vertical fins on a surface of a substrate;

an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, wherein a sidewall of the L-shaped or U-shaped spacer trough is on a sidewall of at least one of the one or more vertical fins; and

a gate dielectric layer on the sidewall of the at least one of the one or more vertical fins and directly on a trough surface and a side and a top surface of the sidewall of the L-shaped or U-shaped spacer trough.

2. The semiconductor device of claim 1 , wherein the material of the L-shaped or U-shaped spacer trough is silicon nitride (SiN).

3. The semiconductor device of claim 1 , further comprising, a liner between the L-shaped or U-shaped spacer trough and at least one of the one or more vertical fins.

4. The semiconductor device of claim 3 , wherein the material of the liner is silicon oxide (SiO).

5. The semiconductor device of claim 3 , wherein the sidewall of the L-shaped or U-shaped spacer trough has an inside sidewall extending a height above the trough surface in the range of about 1 nm to about 5 nm.

6. The semiconductor device of claim 5 , wherein the liner is L-shaped or U-shaped.

7. The semiconductor device of claim 5 , further comprising a work function layer on the gate dielectric layer, and a gate fill layer on the work function layer to form a gate structure.

8. The semiconductor device of claim 7 , further comprising a top source/drain on the top surface of the at least one of the one or more vertical fins, and a bottom source/drain below the at least one of the one or more vertical fins.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2017
From: BI, ZHENXING; DEVARAJAN, THAMARAI S.; PRANATHARTHIHARAN, BALASUBRAMANIAN; MEHTA, SANJAY C.; SANKARAPANDIAN, MUTHUMANICKAM
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041184/0496 →
Continuity (1)
Related Publication 20180226489A1 · Aug 9, 2018
Cited By (1)
US 12,400,910