Method for forming semiconductor device with monoclinic crystalline metal oxide capping layer
A method includes forming a semiconductor fin protruding over a substrate; forming an isolation structure over the substrate; depositing a first metal oxide layer over the isolation structure; depositing a first oxide layer over the first metal oxide layer; depositing a second metal oxide layer over the first oxide layer, in which the first metal oxide layer and the second metal oxide layer comprise amorphous structures; performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer; after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from the amorphous structures into crystalline structures; forming a gate structure over the semiconductor fin; and forming source/drain structures over the substrate and on opposite sides of the gate structure.
1. A method, comprising:
forming a semiconductor fin protruding over a substrate;
forming an isolation structure over the substrate;
depositing a first metal oxide layer over the isolation structure;
depositing a first oxide layer over the first metal oxide layer;
depositing a second metal oxide layer over the first oxide layer, wherein the first metal oxide layer and the second metal oxide layer comprise amorphous structures;
performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer;
after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from the amorphous structures into crystalline structures;
forming a gate structure over the semiconductor fin; and
forming source/drain structures over the substrate and on opposite sides of the gate structure.
2. The method of claim 1 , further comprising:
depositing a second oxide layer over the second metal oxide layer; and
depositing a third metal oxide layer over the second oxide layer, wherein the CMP process remove an entirety of the second oxide layer and the third metal oxide layer from the substrate.
3. The method of claim 1 , wherein forming the isolation structure comprises:
depositing a first isolation film over the substrate; and
depositing a second isolation film over the first isolation film, wherein the second isolation film is made of a different material than the first isolation film.
4. The method of claim 3 , further comprising performing an etching back process to the isolation structure prior to depositing the first metal oxide layer, wherein the first isolation film has a higher etching resistance to the etching back process than that of the second isolation film, such that a top surface of the second isolation film is lower than a top surface of the first isolation film after the etching back process is completed.
5. The method of claim 1 , wherein an air gap is formed in the second metal oxide layer during depositing the second metal oxide layer.
6. The method of claim 1 , wherein the first oxide layer has a lower dielectric constant than those of the first metal oxide layer and the second metal oxide layer.
7. The method of claim 1 , further comprising etching back the isolation structure such that the isolation structure has a concave top surface.
8. The method of claim 1 , further comprising forming a shallow trench isolation (STI) structure over the substrate prior to forming the isolation structure, wherein isolation structure is in contact with a top surface of the STI structure.
9. The method of claim 1 , further comprising forming a semiconductor layer along a sidewall of the semiconductor fin prior to depositing the first metal oxide layer, wherein the first metal oxide layer is in contact with the semiconductor layer.
10. The method of claim 1 , wherein the annealing process is performed under a temperature in a range from about 700° C. to about 1300° C., the annealing process is performed for a duration in a range from 0.1 ms to about 300s, and the annealing process is performed under a pressure in a range from about 5 torr to about 1000 torr.
11. A method, comprising:
forming first and second semiconductor layers alternately arranged over a substrate;
depositing a third semiconductor layer along sidewalls of the first and second semiconductor layers;
depositing a first isolation film over the substrate and along a sidewall of the third semiconductor layer;
depositing a second isolation film over the first isolation film;
performing an etching back process to the first and second isolation films, wherein the first isolation film has a higher etching resistance to the etching back process than that of the second isolation film, such that a top surface of the first isolation film is higher than a top surface of the second isolation film after the etching back process is completed;
depositing a first metal oxide layer over the first and second isolation films;
depositing a first oxide layer over the first metal oxide layer;
depositing a second metal oxide layer over the first oxide layer, wherein an air gap is formed in the second metal oxide layer;
removing the first semiconductor layers;
forming a gate structure wrapping the second semiconductor layers; and
forming source/drain structures over the substrate and on opposite sides of the gate structure.
12. The method of claim 11 , further comprising:
performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer; and
after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from amorphous structures into crystalline structures.
13. The method of claim 11 , further comprising:
depositing a second oxide layer over the second metal oxide layer; and
depositing a third metal oxide layer over the second oxide layer.
14. The method of claim 11 , wherein removing the first semiconductor layers further removes the third semiconductor layer.
15. The method of claim 11 , wherein the first oxide layer is thinner than the first metal oxide layer and the second metal oxide layer.
16. A method, comprising:
forming a semiconductor layer over a substrate;
forming source/drain structures over the substrate and on opposite sides of the semiconductor layer;
forming an isolation structure over the substrate; and
forming a capping layer over the isolation structure, wherein the capping layer comprises:
a first metal oxide layer, wherein crystalline phases of the first metal oxide layer comprise a monoclinic phase, and the monoclinic phase of the crystalline phases of the first metal oxide layer has a highest percentage among the crystalline phases of the first metal oxide layer;
an oxide layer; and
a second metal oxide layer; and
forming a gate structure wrapping around the semiconductor layer and along the isolation structure and the capping layer.
17. The method of claim 16 , wherein the crystalline phases of the first metal oxide layer further comprise a tetragonal phase, a cubic phase, and an orthorhombic phase.
18. The method of claim 16 , wherein the second metal oxide layer comprises an air gap.
19. The method of claim 16 , wherein the first metal oxide layer and the second metal oxide layer are made of a same material that has a higher dielectric constant than that of the oxide layer.
20. The method of claim 16 , further comprising performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the oxide layer, and the second metal oxide layer prior to forming the gate structure.