Dielectric gap-filling process for semiconductor device
View Patent ↗A semiconductor device and a method of forming the same are provided. The method includes forming a trench in a substrate. A liner layer is formed along sidewalls and a bottom of the trench. A silicon-rich layer is formed over the liner layer. Forming the silicon-rich layer includes flowing a first silicon precursor into a process chamber for a first time interval, and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval. The second time interval is different from the first time interval. The method further includes forming a dielectric layer over the silicon-rich layer.
1. A device comprising:
a semiconductor strip supported by a substrate;
a gate structure along sidewalls and a top surface of the semiconductor strip;
a source/drain region adjacent the gate structure and extending into the semiconductor strip;
a first liner extending along a sidewall of the gate structure and a top surface of the source/drain region;
a first silicon-rich layer over the first liner; and
a first dielectric layer over the first silicon-rich layer.
2. The device of claim 1 , wherein silicon content of the first silicon-rich layer is between about 30 atomic % and about 40 atomic %.
3. The device of claim 1 , wherein the first silicon-rich layer comprises silicon oxide.
4. The device of claim 1 , further comprising:
an isolation region over the substrate and adjacent the semiconductor strip, the isolation region comprising:
a second liner extending along the sidewalls of the semiconductor strip and a top surface of the substrate;
a second silicon-rich layer over the second liner; and
a second dielectric layer over the second silicon-rich layer.
5. The device of claim 4 , wherein silicon content of the second silicon-rich layer is between about 30 atomic % and about 40 atomic %.
6. The device of claim 4 , wherein the second silicon-rich layer comprises silicon oxide.
7. The device of claim 4 , wherein the second silicon-rich layer and the second dielectric layer comprise a same material.
8. A device comprising:
a substrate;
a semiconductor strip extending from the substrate;
an isolation region over the substrate and adjacent the semiconductor strip;
a gate structure over the semiconductor strip;
a first liner extending along a sidewall of the gate structure and a top surface of the isolation region;
a first silicon-rich layer over the first liner; and
a first dielectric layer over the first silicon-rich layer, wherein a top surface of the gate structure is level with a top surface of the first dielectric layer.
9. The device of claim 8 , wherein silicon content of the first silicon-rich layer is between about 30 atomic % and about 40 atomic %.
10. The device of claim 8 , wherein the first silicon-rich layer comprises silicon oxide.
11. The device of claim 8 , wherein the isolation region comprises:
a second dielectric layer; and
a second silicon-rich layer lining sidewalls and a bottom surface of the second dielectric layer.
12. The device of claim 11 , wherein the second silicon-rich layer has a thickness between 3 Å and 5 Å.
13. The device of claim 11 , wherein the second silicon-rich layer and the second dielectric layer comprise a same material.
14. The device of claim 11 , wherein silicon content of the second silicon-rich layer is between about 30 atomic % and about 40 atomic %.
15. A device comprising:
a substrate;
a semiconductor strip extending away from a first surface of the substrate;
an isolation region over the substrate and adjacent the semiconductor strip, the isolation region comprising:
a first liner extending along a sidewall of the semiconductor strip and the first surface of the substrate;
a first silicon-rich layer over the first liner; and
a first dielectric layer over the first silicon-rich layer;
a gate structure over the semiconductor strip;
a second liner extending along a sidewall of the gate structure and a top surface of the isolation region;
a second silicon-rich layer over the second liner; and
a second dielectric layer over the second silicon-rich layer.
16. The device of claim 15 , wherein the first liner has a thickness between 20 Å and 40 Å.
17. The device of claim 15 , wherein silicon content of the first silicon-rich layer is between about 30 atomic % and about 40 atomic %.
18. The device of claim 15 , wherein the first silicon-rich layer comprises an oxide material.
19. The device of claim 15 , wherein the first silicon-rich layer has a thickness between 8 Å and 12 Å.
20. The device of claim 15 , wherein silicon content of the second silicon-rich layer is between about 30 atomic % and about 40 atomic %.