HDP fill with reduced void formation and spacer damage

1. A semiconductor device, comprising:

a plurality of high aspect ratio gate structures formed adjacent to one another and forming gaps therebetween, the high aspect ratio gate structures including a top surface;

spacers formed on sidewalls of the high aspect ratio structures, the spacers having a higher etch resistance than SiN in a selective oxide etch to maintain dimensions of the spacers during etch processes, wherein each of the plurality of high aspect ratio structures includes a replacement metal gate between the spacers, the replacement metal gate including a high-k dielectric layer and a metal fill layer;

the gaps being filled with:

a protection layer formed on the spacers to a height on the spacers;

a flowable dielectric formed to below the height within the protection layer; and

a high density plasma dielectric fill above the height; and

contacts formed through the high density plasma dielectric fill, the flowable dielectric and the protection layer to connect to source and drain regions.

2. The device as recited in claim 1 , wherein the spacers include SiBCN.

3. The device as recited in claim 1 , wherein the spacers includes a thickness of 12 nm or less to increase a gap size between each of the high aspect ratio gate structures without altering a pitch between each of the high aspect ratio gate structures.

4. The device as recited in claim 1 , wherein the protection layer includes a nitride.

5. The device as recited in claim 1 , wherein the plurality of high aspect ratio structures includes a high to width ratio greater than 1:1.

6. The device as recited in claim 1 , wherein the plurality of high aspect ratio structures includes a high to width ratio greater than 3:1.

7. The device as recited in claim 1 , wherein each of the plurality of high aspect ratio structures includes at least a gate material and a first dielectric layer.

8. The device as recited in claim 7 , wherein the first dielectric layer includes a material having a higher etch resistance than SiN.

9. The device as recited in claim 7 , wherein the first dielectric layer includes SiBCN.

10. The device as recited in claim 7 , wherein the spacers exceed a height of the gate material and the first dielectric layer such that the spacers form horns on top corners of the spacers.

11. The device as recited in claim 1 , wherein the contacts include a contact liner and a metal contact.

12. The device as recited in claim 1 , wherein the source and drain regions are disposed on opposite sides of each of the plurality of high aspect ratio gate structures and adjacent to the spacers.

13. The device as recited in claim 1 , wherein a portion of the protection layer is disposed over the source and drain regions to separate the flowable dielectric from the source and drain regions.

14. A method for filling gaps between structures in a semiconductor device, comprising:

forming a plurality of high aspect ratio structures adjacent to one another to provide gaps therebetween, wherein forming the plurality of high aspect ratio structures includes patterning a stack of layers including at least a gate material, a first dielectric layer and a hard mask layer;

forming a spacer dielectric layer over the high aspect ratio structures;

removing the spacer dielectric layer from horizontal surfaces to form spacers on sidewalls of the high aspect ratio structures;

forming source and drain regions adjacent to the spacers;

conformally depositing a protection layer over the high aspect ratio structures and the source and drain regions;

filling the gaps with a flowable dielectric;

recessing the flowable dielectric to a height along the sidewalls of the high aspect ratio structures such that the protection layer protects the spacers of the high aspect ratio structures; and

selectively removing the protection layer above the height to maintain a thickness of the spacers.

15. The method as recited in claim 14 , wherein forming the spacer dielectric layer over the high aspect ratio structures includes conformally depositing the spacer dielectric layer with a thickness of 12 nm or less to increase a gap size between high aspect ratio structures without altering a pitch between the high aspect ratio structures.

16. The method as recited in claim 15 , further comprising filling the gaps by a high density plasma fill, wherein filling the gaps by the high density plasma fill includes avoiding formation of voids by providing the gap size that has been increased.

17. The method as recited in claim 14 , wherein selectively removing the protection layer includes forming horns on top corners of each of the plurality of high aspect ratio structures.

18. The method as recited in claim 14 , further comprising forming contact holes by etching through the flowable dielectric and the protection layer.

19. A semiconductor device, comprising:

a plurality of high aspect ratio gate structures formed adjacent to one another and forming gaps therebetween, the high aspect ratio gate structures including a top surface;

spacers formed on sidewalls of the high aspect ratio structures, the spacers having a higher etch resistance than SiN in a selective oxide etch to maintain dimensions of the spacers during etch processes;

the gaps being filled with:

a protection layer formed on the spacers to a height on the spacers;

a flowable dielectric formed to below the height within the protection layer; and

a high density plasma dielectric fill above the height; and

contacts formed through the high density plasma dielectric fill, the flowable dielectric and the protection layer to connect to source and drain regions, wherein a portion of the protection layer is disposed over the source and drain regions to separate the flowable dielectric from the source and drain regions.