Runtime compiler environment with dynamic co-located code execution
A system is provided for monitoring, regenerating and replacing the code of running applications with semantically equivalent, specialized code versions that reflect the demands of the execution environment. The system includes a co-designed compiler and runtime system that virtualizes a selected set of edges in a host program, where these edges provide hooks through which the runtime system may redirect execution into an intermediate representation utilized to optimize introspective and extrospective processes.
1. A computer-implemented method of executing a host application code using one or more runtime processors and using co-located code instructions accessible to the one or more runtime processors, the method comprising:
monitoring the host application code introspectively during runtime, the host application code including a plurality of functions and/or code regions, and/or monitoring extrospectively for changes in a runtime environment;
identifying one or more control edges within the host application code, where the one or more edges are redirection points for a subset of the plurality of functions and/or code regions;
caching a code variant for each function and/or code region associated with the one or more control edges; and
during runtime execution of the host application code, redirecting code execution out of host application code at each of the one or more control edges to execute the cached code variant corresponding to the function and/or code region associated with the one or more edges and redirecting code execution back into the host application code after completion of the executed cached code variant, wherein redirecting code execution occurs in response to a trigger determined from the introspective monitoring and/or the extrospective monitoring.
2. The method of claim 1 , wherein introspective monitoring includes identifying a hot code region.
3. The method of claim 1 , wherein extrospective monitoring includes monitoring for changes in the input/load fluctuation, changes in the starting or stopping of co-running applications, phase changes in the host application code, and/or phase changes in a runtime execution environment.
4. The method of claim 3 , wherein the phase changes in the host application code comprise changes in the instructions per cycle or branches retired per cycle.
5. The method of claim 3 , wherein the phase changes in hardware performance comprise cache misses, bandwidth usage, queries per second, and/or latency.
6. The method of claim 1 , further comprising:
identifying, through the monitoring of the host application during runtime, that one or more performance slowdown conditions are present during runtime; and
determining (i) when to identify the one or more control edges within the application code, (ii) the number of the one or more control edges to be identify, and (iii) the number of code variants to cache so that the one or more performance slowdown conditions are reversed as a result of the redirecting code execution out of host application code.
7. The method of claim 1 , further comprising caching the code variant for each function and/or code region associated with the one or more control edges in a low-level virtual machine state.
8. The method of claim 1 , further comprising caching the code variant for each function and/or code region associated with the one or more control edges buy updating a metadata table in the host application code, the metadata table mapping of subset of the plurality of functions and/or code regions to the one or more control edges.
9. A system comprising:
one or more processors and one or more memories, the one or more memories storing instructions that when executed by the one or more processors, cause the one or more processors to:
monitor host application code introspectively during runtime, the host application code including a plurality of functions and/or code regions and/or monitor extrospectively for changes in a runtime environment;
identify one or more control edges within the host application code, where the one or more edges are redirection points for a subset of the plurality of functions and/or code regions;
cache a code variant for each function and/or code region associated with the one or more control edges; and
during runtime execution of the host application code, redirect code execution out of host application code at each of the one or more control edges to execute the cached code variant corresponding to the function and/or code region associated with the one or more edges and redirecting code execution back into the host application code after completion of the executed cached code variant, wherein redirecting code execution occurs in response to a trigger determined from the introspective monitoring and/or the extrospective monitoring.
10. The system of claim 9 , wherein the one or more memories further store instructions that when executed by the one or more processors, cause the one or more processors to identify a hot code region.
11. The system of claim 10 , wherein extrospective monitoring includes monitoring for changes in the input/load fluctuation, changes in the starting or stopping of co-running applications, phase changes in the host application code, and/or phase changes in a runtime execution environment.
12. The system of claim 11 , wherein the phase changes in the host application code comprise changes in the instructions per cycle or branches retired per cycle.
13. The system of claim 11 , wherein the phase changes in hardware performance comprise cache misses, bandwidth usage, queries per second, and/or latency.
14. The system of claim 9 , wherein the one or more memories further store instructions that when executed by the one or more processors, cause the one or more processors to:
identify, through the monitoring of the host application during runtime, that one or more performance slowdown conditions are present during runtime;
determine (i) when to identify the one or more control edges within the application code, (ii) the number of the one or more control edges to be identify, and (iii) the number of code variants to cache so that the one or more performance slowdown conditions are reversed as a result of the redirecting code execution out of host application code.
15. The system of claim 9 , wherein the one or more memories further store instructions that when executed by the one or more processors, cause the one or more processors to cache the code variant for each function and/or code region associated with the one or more control edges in a low-level virtual machine state.
16. The system of claim 9 , wherein the one or more memories further store instructions that when executed by the one or more processors, cause the one or more processors to cache the code variant for each function and/or code region associated with the one or more control edges buy updating a metadata table in the host application code, the metadata table mapping of subset of the plurality of functions and/or code regions to the one or more control edges.