Integration process of finFET spacer formation
View Patent ↗A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel plasma process, an oxide layer is grown over sidewall materials and low energy plasma gas is used for the over-etching of the corner areas of the sidewalls. The oxide layer can effectively protect the sidewall materials during the over-etching by the low energy plasma gas and thus to reduce the aforementioned CD losses introduced by the low energy plasma gas. This improved low energy plasma etching technique can protect the fin structure from CD losses as compared to the conventional low energy plasma process, and also avoid damaging fin silicon structure with reduced Si losses as compared to the conventional high energy plasma process.
1. A method for fabricating 3D fin field-effect transistor (FinFET) device , the method comprising:
providing a fin shaped silicon over a substrate;
providing a gate structure wrapped around three sides of the fin shaped silicon;
depositing a silicon-nitride (SiN) layer over an entire surface of the gate structure and the fin shaped silicon;
depositing an oxide layer over an entire surface of the SiN layer, the oxide layer comprising a first portion over a tip of the gate structure, a second portion along a side of the gate structure in a vertical direction, and a third portion over the fin shaped silicon;
performing an oxide etch process to remove the first portion of the oxide layer, a bottom portion of the second portion of the oxide layer, and the third portion of the oxide layer, leaving a top portion of the second portion of the oxide layer;
performing an SiN etching process to remove portions of the SiN layer over the tip of the gate structure and over the fin shaped silicon; and
performing an oxide removal process to remove the top portion of the second portion of the oxide layer such that the SiN layer in the vertical direction forms at least a sidewall spacer to the gate structure.
2. The method of claim 1 , wherein the thickness of the oxide layer is between 10 Angstroms to 100 Angstroms.
3. The method of claim 1 , wherein the oxide layer comprises silicon oxide.
4. The method of claim 1 , wherein the oxide layer is deposited using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.
5. The method of claim 1 , wherein the oxide etch process includes a selectively dry etching step that selectively removes the third portion of the oxide layer.
6. The method of claim 5 , the selectively dry etching step removes the oxide layer on a surface of a hard mask cap formed over the gate structure.
7. The method of claim 1 , wherein the SiN etching process is a plasma process.
8. The method of claim 7 , wherein the energy of the low energy plasma gas employed in the plasma process is between 10 eV to 100 eV.
9. The method of claim 7 , further comprising performing an over-etching process to smooth at least a corner formed around the SiN layer and the fin shaped silicon.
10. The method of claim 1 , wherein the oxide removal process is a wet etching process or a process employing SiCoNi.