Stress relief in semiconductor wafers
Methods for compensating for bow in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming an adhesion layer on the backside of the wafer, and forming a stress compensation layer on the adhesion layer.
1. A method of compensating for bow in a semiconductor wafer comprising:
obtaining a semiconductor wafer including an epitaxial layer formed on a top major surface of a semiconductor substrate, the epitaxial layer causing a wafer bow across the surface of the semiconductor substrate:
applying an adhesion layer across an exposed major surface of the semiconductor wafer; and
depositing a stress compensation layer over the adhesion layer, the stress compensation layer exhibiting a high stress state and formed to a thickness sufficient to substantially reduce the amount of wafer bow.
2. The method as defined in claim 1 wherein the adhesion layer is applied across an exposed major surface of the epitaxial layer.
3. The method as defined, in claim 1 wherein the adhesion layer is applied across an exposed bottom surface of the semiconductor substrate.
4. The method as defined in claim 1 wherein the adhesion layer comprises a dielectric material and is applied to a thickness no greater than 0.5 μm.
5. The method as defined in claim 4 wherein the adhesion layer dielectric material is selected from the group consisting of SiO 2 and SiN.
6. The method as defined in claim 1 wherein the adhesion layer comprises a metal and is applied a thickness no greater than 0.02 μm.
7. The method as defined in claim 6 wherein the adhesion layer metal is selected from the group consisting of: titanium, titanium nitride, tungsten, tantalum, aluminum and gold.
8. The method as defined in claim 1 wherein the stress compensation layer is deposited using a chemical vapor deposition process to impart a defined high stress condition within the deposited layer.
9. The method as defined in claim 8 wherein a plasma chemical or deposition (PCVD) process is used.
10. The method as defined in claim 8 wherein a plasma-enhanced chemical vapor deposition (PECVD) process is used.
11. The method as defined in claim 8 wherein a deposition process temperature is selected to be no, greater than subsequent device fabrication temperatures.
12. The method as defined in claim 1 wherein the stress compensation layer comprises a dielectric material.
13. The method as defined in claim 12 wherein the dielectric material is selected from the group consisting of: SiO2 and SiN.
14. The method as defined in claim 1 wherein the stress compensation layer comprises a metal selected from the group consisting of titanium, tungsten, nickel, aluminum, tantalum, and allows thereof.
15. The method as defined in claim 1 , wherein the method includes the additional steps of
prior to applying the adhesion layer, measuring an initial wafer bow exhibited by the obtained semiconductor wafer;
subsequent to depositing the stress compensation layer, measuring a resultant wafer bow remaining in the structure; and
if the remaining wafer bow is above a predetermined threshold, modifying the thickness of the stress compensation layer.
16. The method as defined in claim 15 , wherein the thickness of the stress compensation layer is increased to reduce the resultant wafer bow.
17. The method as defined in claim 15 , wherein the thickness of the stress compensation layer is decreased to reduce the resultant wafer bow.
18. A bow-compensated semiconductor wafer comprising:
a substrate of a semiconductor material, the substrate having first and second major surfaces;
an epitaxial layer formed on the first major surface of the substrate, the combination of the substrate and the epitaxial layer creating a wafer bow across the semiconductor wafer;
an adhesion layer formed on, an exposed major surface of the semiconductor wafer; and
a stress compensation layer formed on the adhesion layer, the stress compensation layer exhibiting a high stress state and formed to a thickness sufficient to reduce the created wafer bow.
19. The bow-compensated semiconductor wafer as defined in claim 18 wherein the adhesion layer comprises a metal layer formed on the second major surface of the substrate.
20. The bow-compensated semiconductor wafer as defined in claim 19 wherein the stress compensation layer comprises a PCVD dielectric layer deposited on the metal adhesion layer.