Semiconductor package and a method for manufacturing a semiconductor device
A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.
1. A semiconductor package, comprising:
a die pad;
a plurality of external connection terminals located around the die pad;
a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and
a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals,
wherein the outer terminal includes a top surface and a bottom surface, being on flat planes substantially parallel to each other, and a side surface, being a surface excluding the top surface and the bottom surface,
the side surface includes a first side surface, a second side surface, and a third side surface,
the first side surface and the second side surface face the side surface of adjoining outer terminal or are parallel surface to the first side surface or the second side surface facing the side surface of adjoining outer terminal,
the third side surface is a surface connecting the first side surface to the second side surface,
the third side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated, and
the outer terminal of each of the plurality of external connection terminals includes a protruding portion at the side surface, and the first area includes an apex portion of the protruding portion.
2. The semiconductor package according to claim 1 , wherein the first area corresponds to the side surface of the outer terminal.
3. A semiconductor package, comprising:
a die pad;
a plurality of external connection terminals located around the die pad;
a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and
a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals,
wherein the outer terminal includes a top surface and a bottom surface, being on flat planes substantially parallel to each other, and a side surface, being a surface excluding the top surface and the bottom surface,
the side surface includes a first side surface, a second side surface, and a third side surface,
the first side surface and the second side surface face the side surface of adjoining outer terminal or are parallel surface to the first side surface or the second side surface facing the side surface of adjoining outer terminal,
the third side surface is a surface connecting the first side surface to the second side surface,
the third side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated, and
the outer terminal of each of the plurality of external connection terminals includes a tapering portion at the side surface, and the first area includes the tapering portion.