Methods of forming a protection layer on a semiconductor device and the resulting device
One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent opposite sides of the gate structure, and a multi-layer gate cap structure positioned above the gate structure and the upper surface of the spacers. The multi-layer gate cap structure includes a first gate cap material layer positioned on an upper surface of the gate structure and on the upper surfaces of the first and second spacers, a first high-k protection layer positioned on an upper surface of the first gate cap material layer and a second gate cap material layer positioned on an upper surface of the high-k protection layer. The first and second gate cap layers comprise different materials than the first high-k protection layer.
1. A transistor device, comprising:
a gate structure;
first and second spacers positioned adjacent opposite sides of said gate structure, said first and second spacers having upper surfaces; and
a multi-layer gate cap structure positioned above said gate structure and said upper surfaces of said first and second spacers, wherein said multi-layer gate cap structure comprises:
a first gate cap material layer positioned on an upper surface of said gate structure and on said upper surfaces of said first and second spacers;
a first high-k protection layer positioned on an upper surface of said first gate cap material layer; and
a second gate cap material layer positioned on an upper surface of said first high-k protection layer, wherein said first and second spacers, said first and second gate cap layers, and said high-k protection layer comprise dielectric materials, and said first and second gate cap layers comprise different materials than said first high-k protection layer.
2. The device of claim 1 , wherein said upper surface of said first gate cap material layer is non-planar.
3. The device of claim 2 , wherein said upper surface of said first high-k protection layer is non-planar.
4. The device of claim 3 , wherein an upper surface of said second gate cap material layer is substantially planar.
5. The device of claim 1 , wherein said first gate cap material layer is made of silicon nitride, said first high-k protection layer is made of hafnium oxide and said second gate cap material layer is made of silicon nitride.
6. The device of claim 1 , further comprising a second high-k protection layer contacting a portion of a sidewall of said first spacer and a sidewall portion of said first gate cap material layer.
7. The device of claim 6 , further comprising first and second source/drain regions positioned adjacent said first and second spacers, respectively, wherein said second high-k protection layer contacts an upper surface of said first source/drain region.
8. The device of claim 7 , wherein said first and second high-k protection layers are comprised of the same high-k material.
9. The device of claim 1 , further comprising:
a layer of insulating material disposed above said multi-layer gate cap structure; and
a contact structure positioned in said layer of insulating material and contacting said gate structure, said first gate cap material layer, and a sidewall portion of said second spacer.
10. A transistor device, comprising:
a gate structure;
first and second spacers positioned adjacent opposite sides of said gate structure, said first and second spacers having upper surfaces;
first and second source/drain regions positioned adjacent said first and second spacers, respectively;
a first high-k protection layer contacting a portion of a sidewall of said first spacer and an upper surface of said first source/drain region; and
a multi-layer gate cap structure positioned above said gate structure and said upper surfaces of said first and second spacers, wherein said multi-layer gate cap structure comprises:
a first gate cap material layer positioned on an upper surface of said gate structure and on said upper surfaces of said first and second spacers;
a second high-k protection layer positioned on an upper surface of said first gate cap material layer; and
a second gate cap material layer positioned on an upper surface of said second high-k protection layer, wherein said first and second spacers, said first and second gate cap layers, and said high-k protection layer comprise dielectric materials, and said first and second gate cap layers comprise different materials than said second high-k protection layer.
11. The device of claim 10 , wherein said first high-k protection layer contacts a sidewall portion of said first gate cap material layer.
12. The device of claim 10 , wherein said upper surface of said first gate cap material layer is non-planar.
13. The device of claim 12 , wherein said upper surface of said second high-k protection layer is non-planar.
14. The device of claim 13 , wherein an upper surface of said second gate cap material layer is substantially planar.
15. The device of claim 10 , wherein said first gate cap material layer is made of silicon nitride, said first and second high-k protection layers are made of hafnium oxide and said second gate cap material layer is made of silicon nitride.
16. The device of claim 10 , wherein said first and second high-k protection layers are comprised of the same high-k material.
17. The device of claim 10 , further comprising:
a layer of insulating material disposed above said multi-layer gate cap structure; and
a contact structure positioned in said layer of insulating material and contacting said gate structure, said first gate cap material layer and a sidewall portion of said second spacer.