Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.
1. A three-dimensional memory device comprising:
a vertically alternating stack of electrically conductive layers and insulating layers located over a source semiconductor layer over a substrate;
an array of memory stack structures that extend through the vertically alternating stack and into an upper portion of the source semiconductor layer, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel, wherein a lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure that adjoins a top end of the bulging portion;
at least one source strap structure contacting a respective subset of the semiconductor channels of the memory stack structures at a level of the bulging portion of each memory stack structure, wherein the at least one source strap structure comprises source strap rails;
a gate dielectric layer overlying the source strap rails and laterally surrounding the memory stack structures; and
a doped semiconductor layer underlying the vertically alternating stack and overlying the gate dielectric layer and laterally surrounding the memory stack structures,
wherein the memory film of each memory stack structure includes a lateral opening through which a respective source strap rail extends to provide physical contact between a respective semiconductor channel and the respective source strap rail.
2. The three-dimensional memory device of claim 1 , wherein the bulging portion comprises:
an annular top surface having an inner periphery that adjoins an outer periphery of the overlying portion of the respective memory stack structure;
a sidewall having an upper periphery that adjoins an outer periphery of the annular top surface; and
a planar bottom surface contacting a horizontal surface of the source semiconductor layer.
3. The three-dimensional memory device of claim 1 , further comprising dielectric rails located between neighboring pairs of the source strap rails, wherein the memory film of each memory stack structure contacts a sidewall of a respective one of the dielectric rails.
4. The three-dimensional memory device of claim 1 , wherein:
the source strap rails contact a respective portion of a planar top surface of the source semiconductor layer; and
the source strap rails comprise a doped semiconductor material having a doping of a same conductivity type as the source semiconductor layer.
5. The three-dimensional memory device of claim 1 , wherein:
the gate dielectric layer overlies top surfaces of the bulging portions of the memory stack structures; and
the doped semiconductor layer comprises source select gate electrodes of the memory stack structures.
6. The three-dimensional memory device of claim 1 , wherein:
the gate dielectric layer laterally surrounds the bulging portions of the memory stack structures; and
a top surface of the doped semiconductor layer is within a same horizontal plane as top surfaces of the bulging portions.
7. The three-dimensional memory device of claim 1 , wherein:
the source strap rails laterally extend along a first horizontal direction; and
the three-dimensional memory device further comprises an insulating wall structure that vertically extends through the vertically alternating stack and laterally extends along a second horizontal direction that is different from the first horizontal direction and straddles each of the source strap rails.
8. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.
9. A three-dimensional memory device comprising:
a vertically alternating stack of electrically conductive layers and insulating layers located over a source semiconductor layer over a substrate;
an array of memory stack structures that extend through the vertically alternating stack and into an upper portion of the source semiconductor layer, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel, wherein a lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure that adjoins a top end of the bulging portion; and
at least one source strap structure contacting a respective subset of the semiconductor channels of the memory stack structures at a level of the bulging portion of each memory stack structure, wherein the at least one source strap structure comprises source strap rails, the source strap rails laterally extend along a first horizontal direction, and the memory film of each memory stack structure includes a lateral opening through which a respective source strap rail extends to provide physical contact between a respective semiconductor channel and the respective source strap rail; and
an insulating wall structure that vertically extends through the vertically alternating stack and laterally extends along a second horizontal direction that is different from the first horizontal direction and straddles each of the source strap rails.
10. The three-dimensional memory device of claim 9 , wherein the bulging portion comprises:
an annular top surface having an inner periphery that adjoins an outer periphery of the overlying portion of the respective memory stack structure;
a sidewall having an upper periphery that adjoins an outer periphery of the annular top surface; and
a planar bottom surface contacting a horizontal surface of the source semiconductor layer.
11. The three-dimensional memory device of claim 9 , further comprising dielectric rails located between neighboring pairs of the source strap rails, wherein the memory film of each memory stack structure contacts a sidewall of a respective one of the dielectric rails.
12. The three-dimensional memory device of claim 9 , wherein:
the source strap rails contact a respective portion of a planar top surface of the source semiconductor layer; and
the source strap rails comprise a doped semiconductor material having a doping of a same conductivity type as the source semiconductor layer.
13. The three-dimensional memory device of claim 9 , further comprising:
a gate dielectric layer overlying the source strap rails and laterally surrounding the memory stack structures; and
a doped semiconductor layer underlying the vertically alternating stack and overlying the gate dielectric layer and laterally surrounding the memory stack structures.
14. The three-dimensional memory device of claim 13 , wherein:
the gate dielectric layer overlies top surfaces of the bulging portions of the memory stack structures; and
the doped semiconductor layer comprises source select gate electrodes of the memory stack structures.
15. The three-dimensional memory device of claim 13 , wherein:
the gate dielectric layer laterally surrounds the bulging portions of the memory stack structures; and
a top surface of the doped semiconductor layer is within a same horizontal plane as top surfaces of the bulging portions.
16. The three-dimensional memory device of claim 9 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.