Replacement low-k spacer

1. A method of forming a semiconductor structure comprising:

forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack;

partially recessing the dummy gate stack;

etching the sacrificial spacer down to the partially recessed dummy gate stack;

etching remaining portions of the sacrificial spacer leaving gaps on sides of a remaining portion of the dummy gate stack;

forming a first low-k spacer portion and a second low-k spacer portion to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity;

etching the first low-k spacer portion and the second low-k spacer portion;

performing a poly pull process on the remaining portions of the dummy gate stack;

forming a replacement metal gate (RMG) structure with the first low-k spacer portion and the second low-k spacer portion; and

forming a low-k cap layer over the RMG structure, wherein a height of the low-k cap layer is reduced to an oxide layer on the substrate.

2. The method of claim 1 , wherein the sacrificial spacer comprises a silicon nitride spacer.

3. The method of claim 1 , wherein the sacrificial spacer comprises a first dielectric spacer portion and a second dielectric spacer portion.

4. The method of claim 3 , wherein forming the dummy gate stack comprises:

forming a source junction on the substrate adjacent the first dielectric spacer portion and a drain junction on the substrate adjacent the second dielectric spacer portion; and

the oxide layer is deposited over the source junction and the drain junction.

5. The method of claim 4 , wherein the first low-k spacer portion and the second low-k spacer portion are etched after forming the RMG structure.

6. The method of claim 5 , wherein chemical-mechanical planarization (CMP) is performed to reduce the height of the low-k cap layer down to the oxide layer.

7. The method of claim 5 , wherein chemical-mechanical planarization (CMP) is performed to reduce the height of the low-k cap layer to the oxide layer, wherein the low-k cap layer completely covers the RMG structure and top portions of the first low-k spacer portion and the second low-k spacer portion.

8. The method of claim 5 , wherein:

the low-k cap layer is formed over the RMG structure and adjacent to the first low-k spacer portion and the second low-k spacer portion.

9. A method of forming a semiconductor structure comprising:

etching a sacrificial spacer down to a partially recessed dummy gate stack formed on a substrate;

forming a first low-k spacer portion and a second low-k spacer portion to fill gaps on sides of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity;

etching the first low-k spacer portion and the second low-k spacer portion;

performing a poly pull process on the dummy gate stack;

performing multiple depositions to form a replacement metal gate (RMG) structure with the first low-k spacer portion and the second low-k spacer portion; and

forming a silicon nitride cap layer over the RMG structure, wherein a height of the silicon nitride cap layer is reduced to an oxide layer on the substrate.

10. The method of claim 9 , wherein the sacrificial spacer comprises a first dielectric spacer portion and a second dielectric spacer portion.

11. The method of claim 9 , wherein the first low-k spacer portion and the second low-k spacer portion are formed prior to forming the RMG structure.

12. The method of claim 11 , wherein:

the silicon nitride cap layer is formed over the RMG structure and between the first low-k spacer portion and the second low-k spacer portion; and

chemical-mechanical planarization (CMP) is performed to reduce the height of the silicon nitride cap layer down to the oxide layer.

13. The method of claim 11 , further comprising:

performing chemical-mechanical planarization (CMP) to reduce a height of the silicon nitride cap layer to the oxide layer formed over the substrate, wherein the silicon nitride cap layer completely covers the RMG structure.

14. The method of claim 11 , wherein the silicon nitride cap layer is formed over the RMG structure and adjacent to the first low-k spacer portion and the second low-k spacer portion.

15. A method of forming a semiconductor structure comprising:

forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack;

partially recessing the dummy gate stack;

etching the sacrificial spacer down to the partially recessed dummy gate stack;

etching remaining portions of the sacrificial spacer leaving gaps on sides of a remaining portion of the dummy gate stack;

forming a low-k spacer portion and a second low-k spacer portion to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity; and

forming a low-k cap layer over a replacement metal gate (RMG) structure and on top of the first low-k spacer portion and the second low-k spacer portion, wherein a height of the low-k cap layer is reduced to an oxide layer on the substrate.

16. The method of claim 15 , wherein the sacrificial spacer comprises a silicon nitride spacer.

17. The method of claim 15 , wherein the sacrificial spacer comprises a first dielectric spacer portion and a second dielectric spacer portion.

18. The method of claim 17 , wherein forming the dummy gate stack comprises:

forming a source junction on the substrate adjacent the first dielectric spacer portion and a drain junction on the substrate adjacent the second dielectric spacer portion; and

the oxide layer is deposited over the source junction and the drain junction.

19. The method of claim 18 , wherein the first low-k spacer portion and the second low-k spacer portion are etched after forming the RMG structure.