IP Library › Granted Patent US 10,147,815
Granted Patent B2
US 10,147,815 · App. 15/463,545 · Granted Dec 4, 2018

Fully silicided linerless middle-of-line (MOL) contact

Inventors: Joshua M. Rubin (Albany, NY); Tenko Yamashita (Schenectady, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/7845H01L21/02063H01L21/2855H01L21/28525H01L21/76805H01L21/76814H01L21/76865H01L21/76889H01L21/76895H01L21/76897H01L23/485H01L23/53271H01L29/401H01L29/41783H01L29/4975H01L29/665H01L29/66553H01L29/66628H01L29/66795H01L29/785H01L29/7848
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Quick Facts
Patent No.
US 10,147,815
App. No.
15/463,545
Granted
Dec 4, 2018
Kind
B2
Abstract

A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.

Claims (17)

1. A method of making a semiconductor device, the method comprising:

forming a source/drain region on a substrate;

disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack comprising a gate spacer along a sidewall of the gate stack;

disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack;

removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern;

filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer;

depositing a metallic layer over the layer of silicon material; and

performing a silicidation process to form a source/drain contact comprising a silicide, the silicide of the source/drain contact extending continuously from the gate spacer to a second gate spacer of an adjacent second gate stack.

2. The method of claim 1 , wherein the silicidation process includes a low temperature annealing process.

3. The method of claim 2 , wherein the low temperature annealing process substantially fully consumes the silicon material to form the metal silicide.

4. The method of claim 3 , wherein the metal silicide is nickel silicide.

5. The method of claim 2 , wherein the low temperature annealing process is performed at a temperature in a range from about 300 to about 600° C.

6. The method of claim 1 , wherein the metallic layer comprises a refractory metal.

7. The method of claim 1 , wherein the source/drain contact consists essentially of the silicide.

8. The method of claim 1 , wherein filling the source/drain contact pattern with the silicide further comprises depositing another silicon layer onto the metallic layer and depositing another a metallic layer onto the another silicon layer.

9. The method of claim 1 , wherein performing the silicidation process comprises performing a thermal annealing process at a temperature in a range from about 300 to about 600° C.

10. The method of claim 1 , further comprising pre-cleaning the source/drain contact pattern after removing a portion of the ILD layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2017
From: RUBIN, JOSHUA M.; YAMASHITA, TENKO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041646/0534 →
Continuity (3)
Continuation 14967736 · Dec 14, 2015
Continuation 14856918 · Sep 17, 2015
Related Publication 20170194202A1 · Jul 6, 2017
Cited By (1)
US 12,363,928