IP Library Granted Patent US 9,941,119
Granted Patent B2
US 9,941,119 · App. 15/468,966 · Granted Apr 10, 2018

Method of forming silicon layer in manufacturing semiconductor device and recording medium

Inventors: Atsushi Moriya (Toyama, JP); Naoharu Nakaiso (Toyama, JP); Yugo Orihashi (Toyama, JP); Kotaro Murakami (Toyama, JP)
Assignee: HITACHI KOKUSAI ELECTRIC INC.
H01L21/02609C23C16/0272C23C16/24C23C16/4408C23C16/45523C23C16/45529C23C16/45544C23C16/46C23C16/52C23C16/56C30B25/04C30B25/165C30B25/186C30B25/20C30B29/06H01L21/0245H01L21/0257H01L21/0262H01L21/02381H01L21/02428H01L21/02513H01L21/02532H01L21/02576H01L21/02579H01L21/02592H01L21/02595H01L21/02598H01L21/02634H01L21/02639H01L21/02645H01L21/02694H01L21/324H01L21/32055H01L27/1085H01L27/10891H01L27/1157H01L27/11582H01L27/0688H01L27/10805H01L27/10873H01L27/11556
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Quick Facts
Patent No.
US 9,941,119
App. No.
15/468,966
Granted
Apr 10, 2018
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

Claims (26)

1. A method of manufacturing a semiconductor device, comprising:

(a) supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and a silicon oxide film are exposed, thereby generating a breaking reaction of chemical bonds between silicon and oxygen contained in the silicon oxide film using the halogen element;

(b) supplying a second process gas containing silicon and not containing a halogen element to the substrate; and

(c) alternately performing (a) and (b), whereby a first silicon layer as an epitaxial silicon layer is formed on the monocrystalline silicon and a second silicon layer differing in crystal structure from the first silicon layer is formed on the silicon oxide film.

2. The method of claim 1 , wherein the first silicon layer and the second silicon layer are formed in parallel.

3. The method of claim 1 , wherein a crystal structure of the second silicon layer is an amorphous, a polycrystal or a mixture of the amorphous and the polycrystal.

4. The method of claim 1 , wherein the first process gas includes silane chloride, and the second process gas includes hydrogenated silane.

5. The method of claim 1 , further comprising:

(d) supplying a third process gas containing silicon to the substrate, whereby a first silicon film is epitaxially grown on the first silicon layer and a second silicon film differing in crystal structure from the first silicon film is grown on the second silicon layer.

6. The method of claim 5 , wherein the first silicon film and the second silicon film are grown in parallel.

7. The method of claim 5 , wherein a recess is formed on the surface of the substrate, the recess including a bottom portion formed of the monocrystalline silicon and a side portion formed of the silicon oxide film.

8. The method of claim 7 , wherein a top portion of the first silicon film is covered with the second silicon film grown from the side portion of the recess, so as to stop epitaxial growth of the first silicon film.

9. The method of claim 7 , wherein a top portion of the first silicon film is covered with the second silicon film grown from the side portion of the recess, so as to form a laminated structure including the first silicon film and the second silicon film laminated on the first silicon film.

10. The method of claim 5 , wherein a crystal structure of the second silicon film is an amorphous, a polycrystal or a mixture of the amorphous and the polycrystal.

11. The method of claim 5 , wherein the third process gas includes hydrogenated silane.

12. The method of claim 5 , wherein a dopant gas together with the third process gas is supplied to the substrate in (c).

13. The method of claim 5 , wherein the second process gas differs in molecular structure from the third process gas.

14. The method of claim 5 wherein a pyrolysis temperature of the second process gas is lower than a pyrolysis temperature of the third process gas.

15. The method of claim 5 , wherein the second process gas is identical in molecular structure with the third process gas.

16. The method of claim 5 , wherein a temperature of the substrate is set at a first temperature in (c), and

a temperature of the substrate is set at a second temperature equal to or higher than the first temperature in (d).

17. The method of claim 1 , wherein the semiconductor device includes a three-dimensional flash memory or a dynamic random access memory.

18. A non-transitory computer-readable recording medium storing a program that causes a substrate processing apparatus, by a computer, to perform processes of:

(a) supplying a first process gas containing silicon and a halogen element to a substrate in a process chamber of the substrate processing apparatus, the substrate having a surface on which monocrystalline silicon and a silicon oxide film are exposed, thereby generating a breaking reaction of chemical bonds between silicon and oxygen contained in the silicon oxide film using the halogen element;

(b) supplying a second process gas containing silicon and not containing a halogen element to the substrate in the process chamber; and

(c) alternately performing (a) and (b), whereby a first silicon layer as an epitaxial silicon layer is formed on the monocrystalline silicon and a second silicon layer differing in crystal structure from the first silicon layer is formed on the silicon oxide film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2018
From: HITACHI KOKUSAI ELECTRIC INC.
To: KOKUSAI ELECTRIC CORPORATION
Reel/Frame 047995/0490 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2017
From: MORIYA, ATSUSHI; NAKAISO, NAOHARU; ORIHASHI, YUGO; MURAKAMI, KOTARO
To: HITACHI KOKUSAI ELECTRIC INC.
Reel/Frame 041751/0961 →
Priority Claims (2)
JP 2014-234401 · Nov 19, 2014 · national
JP 2015-185891 · Sep 18, 2015 · national
Continuity (4)
Continuation 15368337 · Dec 2, 2016
Continuation 15190578 · Jun 23, 2016
Division 14929973 · Nov 2, 2015
Related Publication 20170213727A1 · Jul 27, 2017