Systems and methods for fast delta sigma modulation using parallel path feedback loops
An error feedback system for a delta sigma modulator is disclosed. The error feedback system has an error transfer function where at least k−1 coefficients are set to zero. This allows the error feedback system to be divided into k feedback paths that are performed in parallel at a clock speed that is 1/k of the system clock of the delta sigma modulator (i.e. the rate at which the output of the delta sigma modulator changes).
1. A delta sigma modulator comprising:
a system clock input configured to receive a system clock signal;
a delta sigma modulator input configured to receive an input signal;
a delta sigma modulator output configured to provide a delta sigma modulated output;
a truncator configured to generate the delta sigma modulated output based upon a sum of the input signal and an error feedback signal;
an error feedback system that generates the error feedback signal, where the error feedback system comprises:
k feedback paths that execute in parallel;
wherein each of the k paths are clocked to 1/k clock cycles of the system clock signal and wherein k is an integer equal to or greater than two.
2. The delta sigma modulator of claim 1 , wherein the error feedback system receives as an input a difference between:
the sum of the input signal and an error feedback signal; and
the delta sigma modulated output.
3. The delta sigma modulator of claim 2 wherein the delta sigma modulator is an N order delta sigma modulator where N is an integer equal to or greater than two.
4. The delta sigma modulator of claim 3 wherein each of the k feedback paths include N/k registers that are clocked at a rate 1/k of the system clock signal.
5. The delta sigma modulator of claim 4 wherein each of the k feedback path generates a signal that is a weighted sum of values stored in the N/k registers, where the generated signal is combined with the input to the error feedback system.
6. The delta sigma modulator of claim 4 wherein each of the k feedback path generates a signal that is a weighted sum of values stored in the N/k registers, where the generated signal is quantized by a quantizer to produce an error feedback signal.
7. The delta sigma modulator of claim 3 wherein k is less than N.
8. The delta sigma modulator of claim 1 wherein the truncator is a quantizer.
9. The delta sigma modulator of claim 1 wherein each of the k feedback paths are out of phase with each other.
10. The delta sigma modulator of claim 9 wherein each feedback path generates a separate output and the delta sigma modulator output is selected from the output of a different feedback path every clock cycle of the system clock signal.
11. A method for providing a filtered error signal for a delta sigma modulator comprising:
receiving a system clock signal at a system clock input;
receiving a delta sigma modulator input signal at a delta sigma modulator input;
summing the input signal and an error feedback signal;
truncating the sum of the input signal and an error feedback signal to produce a delta sigma modulator output signal;
outputting the delta sigma modulator output signal on a delta sigma modulator output;
wherein the error feedback signal is generated by an error feedback system using:
k feedback paths that execute in parallel;
wherein each of the k paths are clocked to 1/k clock cycles of the system clock signal and wherein k is an integer equal to or greater than two.
12. The method of claim 11 , wherein the error feedback system receives as an input a difference between:
the sum of the input signal and an error feedback signal; and
the delta sigma modulated output.
13. The method of claim 12 wherein the delta sigma modulator is an N order delta sigma modulator where N is an integer equal to or greater than two.
14. The delta sigma modulator of claim 13 wherein each of the k feedback paths include N/k registers that are clocked at a rate 1/k of the system clock signal.
15. The method of claim 13 wherein each of the k feedback path generates a signal that is a weighted sum of values stored in the N/k registers, where the generated signal is combined with the input to the error feedback system.
16. The method of claim 13 , wherein each of the k feedback path generates a signal that is a weighted sum of values stored in the N/k registers, where the generated signal is quantized by a quantizer to produce an error feedback signal.
17. The method of claim 12 wherein k is less than N.
18. The method of claim 11 , wherein the truncator is a quantizer.
19. The method of claim 11 wherein each of the k feedback paths are out of phase with each other.
20. The method of claim 19 wherein each feedback path generates a separate output and the delta sigma modulator output is selected from the output of a different feedback path every clock cycle of the system clock signal.